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[77.252.46.238]) by smtp.gmail.com with ESMTPSA id a9-20020aa7d749000000b005257da6be23sm9413857eds.75.2023.09.06.23.11.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 06 Sep 2023 23:12:00 -0700 (PDT) Message-ID: Date: Thu, 7 Sep 2023 08:11:58 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.15.0 Subject: Re: [PATCH 2/2] arm: dts: am3517-evm: Enable Ethernet PHY Interrupt Content-Language: en-US To: Adam Ford , linux-omap@vger.kernel.org Cc: aford@beaconembedded.com, =?UTF-8?Q?Beno=c3=aet_Cousson?= , Tony Lindgren , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Derald D. Woods" , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20230907010159.330555-1-aford173@gmail.com> <20230907010159.330555-2-aford173@gmail.com> From: Krzysztof Kozlowski In-Reply-To: <20230907010159.330555-2-aford173@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org On 07/09/2023 03:01, Adam Ford wrote: > The Ethernet PHY interrupt pin is routed to GPIO_58. Create a > PHY node to configure this GPIO for the interrupt to avoid polling. > > Signed-off-by: Adam Ford > > diff --git a/arch/arm/boot/dts/ti/omap/am3517-evm.dts b/arch/arm/boot/dts/ti/omap/am3517-evm.dts > index 738189ddc8d5..19869ef906a8 100644 > --- a/arch/arm/boot/dts/ti/omap/am3517-evm.dts > +++ b/arch/arm/boot/dts/ti/omap/am3517-evm.dts > @@ -172,11 +172,24 @@ hsusb1_phy: hsusb1_phy { > &davinci_emac { > pinctrl-names = "default"; > pinctrl-0 = <ðernet_pins>; > + phy-mode = "rmii"; > + phy-handle = <ðphy0>; > status = "okay"; > }; > > &davinci_mdio { > + #address-cells = <1>; > + #size-cells = <0>; > status = "okay"; > + > + ethphy0: ethernet-phy@0 { > + pinctrl-names = "default"; > + pinctrl-0 = <&enet_phy_pins>; > + compatible = "ethernet-phy-ieee802.3-c22"; > + reg = <0>; > + interrupt-parent = <&gpio2>; > + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; /* gpio_58 */ > + }; > }; > > &dss { > @@ -257,6 +270,12 @@ OMAP3_CORE1_IOPAD(0x2210, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_50mhz_clk */ > >; > }; > > + enet_phy_pins: pinmux_ent_phy_pins { Nope. This looks like pasted from some old downstream tree. Please rewrite downstream code to match upstream. Best regards, Krzysztof