From mboxrd@z Thu Jan 1 00:00:00 1970 From: Kishon Vijay Abraham I Subject: Re: [PATCH v2 08/15] PCI: endpoint: Fix pci_epf_alloc_space to set correct MEM TYPE flags Date: Fri, 15 Feb 2019 11:49:12 +0530 Message-ID: References: <20190114111513.21618-1-kishon@ti.com> <20190114111513.21618-9-kishon@ti.com> <20190211173723.GA31035@e107981-ln.cambridge.arm.com> <20190214162928.GA32523@e107981-ln.cambridge.arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20190214162928.GA32523-4tUPXFaYRHv6sAKXYmQ0tx/iLCjYCKR+VpNB7YpNyf8@public.gmane.org> Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+glpar-linux-rockchip=m.gmane.org-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org To: Lorenzo Pieralisi Cc: Heiko Stuebner , Gustavo Pimentel , Shawn Lin , linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Alan Douglas , Jingoo Han , Bjorn Helgaas , linux-omap-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org List-Id: linux-omap@vger.kernel.org Hi Lorenzo, On 14/02/19 9:59 PM, Lorenzo Pieralisi wrote: > On Wed, Feb 13, 2019 at 07:17:14PM +0530, Kishon Vijay Abraham I wrote: >> Hi Lorenzo, >> >> On 11/02/19 11:07 PM, Lorenzo Pieralisi wrote: >>> On Mon, Jan 14, 2019 at 04:45:06PM +0530, Kishon Vijay Abraham I wrote: >>>> pci_epf_alloc_space() sets the MEM TYPE flags to indicate a 32-bit >>>> Base Address Register irrespective of the size. Fix it here to indicate >>>> 64-bit BAR if the size is > 2GB. >>>> >>>> Signed-off-by: Kishon Vijay Abraham I >>>> --- >>>> drivers/pci/endpoint/pci-epf-core.c | 4 +++- >>>> 1 file changed, 3 insertions(+), 1 deletion(-) >>> >>> This looks like a fix and should me marked as such. Does it work >>> as as standalone patch if it gets backported ? >> >> Yeah, it should work. But the current users doesn't allocate > 2GB and some >> EPC drivers configure their registers based on size. So nothing is broken >> without this patch as such. > > I suspect you mean 4GB (here and the commit log), right ? I am checking > the commit logs, aiming at merging the patches. A 32bit BAR register can support a 'size' of only up to 2GB. Though it can hold a memory address of up to 4GB. This is also mentioned in the PCI Local Bus Specification. "A 32-bit register can be implemented to support a single memory size that is a power of 2 from 16 bytes to 2 GB" Thanks Kishon