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* [PATCH 0/2] OMAP3: introduce DPLL4 Jtype
@ 2009-10-20 10:48 Nishanth Menon
  2009-10-20 10:48 ` [PATCH 1/2] OMAP3: move check_revision above check_features Nishanth Menon
  0 siblings, 1 reply; 8+ messages in thread
From: Nishanth Menon @ 2009-10-20 10:48 UTC (permalink / raw)
  To: linux-omap; +Cc: Nishanth Menon

The patchset introduces jtype DPLLs which as a first stage
introduces it for 3630. 3430 has a previous version of DPLL
and process changes in 3630 neccessitates this for DPLL4

Patchset has been created for linux-omap - tmlind tree

Nishanth Menon (1):
  OMAP3: move check_revision above check_features

Richard Woodruff (1):
  OMAP3:clk - introduce DPLL4 jtype support

 arch/arm/mach-omap2/clock34xx.c         |   45 ++++++++++++++++++++++++++++++-
 arch/arm/mach-omap2/cm-regbits-34xx.h   |    6 +++-
 arch/arm/mach-omap2/id.c                |    5 +++-
 arch/arm/plat-omap/include/plat/clock.h |    3 ++
 arch/arm/plat-omap/include/plat/cpu.h   |    2 +
 5 files changed, 58 insertions(+), 3 deletions(-)

Regards,
Nishanth Menon

^ permalink raw reply	[flat|nested] 8+ messages in thread

* [PATCH 1/2] OMAP3: move check_revision above check_features
  2009-10-20 10:48 [PATCH 0/2] OMAP3: introduce DPLL4 Jtype Nishanth Menon
@ 2009-10-20 10:48 ` Nishanth Menon
  2009-10-20 10:48   ` [PATCH 2/2] OMAP3:clk: introduce DPLL4 jtype support Nishanth Menon
                     ` (2 more replies)
  0 siblings, 3 replies; 8+ messages in thread
From: Nishanth Menon @ 2009-10-20 10:48 UTC (permalink / raw)
  To: linux-omap; +Cc: Nishanth Menon

omap3_check_revision() does not depend on omap3_check_features()
move this above so that we can add logic based on revision
detected in check_features.

Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm/mach-omap2/id.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 1c15112..702d3b4 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -328,8 +328,8 @@ void __init omap2_check_revision(void)
 	if (cpu_is_omap24xx())
 		omap24xx_check_revision();
 	else if (cpu_is_omap34xx()) {
-		omap3_check_features();
 		omap3_check_revision();
+		omap3_check_features();
 		omap3_cpuinfo();
 	}
 	else if (cpu_is_omap44xx()) {
-- 
1.6.3.3


^ permalink raw reply related	[flat|nested] 8+ messages in thread

* [PATCH 2/2] OMAP3:clk: introduce DPLL4 jtype support
  2009-10-20 10:48 ` [PATCH 1/2] OMAP3: move check_revision above check_features Nishanth Menon
@ 2009-10-20 10:48   ` Nishanth Menon
  2009-10-20 14:15     ` Aguirre Rodriguez, Sergio Alberto
  2009-11-03 13:54   ` [PATCH 1/2] OMAP3: move check_revision above check_features Mika Westerberg
  2009-11-12 21:14   ` [APPLIED] " Tony Lindgren
  2 siblings, 1 reply; 8+ messages in thread
From: Nishanth Menon @ 2009-10-20 10:48 UTC (permalink / raw)
  To: linux-omap
  Cc: Richard Woodruff, Vikram Pandita, Sonasath, Moiz Sonasath,
	Nishanth Menon

From: Richard Woodruff <r-woodruff2@ti.com>

DPLL4 for 3630 introduces a changed block requiring
special divisor bits and additional reg fields

To allow for silicons to use this, this is introduced
as a omap3_has_jtype_dpll4() and is enabled for 3630
silicon

Tested with SDP3430, SDP3630

Cc: Vikram Pandita <vikram.pandita@ti.com>
Cc: Sonasath, Moiz Sonasath <m-sonasath@ti.com>
Signed-off-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
 arch/arm/mach-omap2/clock34xx.c         |   45 ++++++++++++++++++++++++++++++-
 arch/arm/mach-omap2/cm-regbits-34xx.h   |    6 +++-
 arch/arm/mach-omap2/id.c                |    3 ++
 arch/arm/plat-omap/include/plat/clock.h |    3 ++
 arch/arm/plat-omap/include/plat/cpu.h   |    2 +
 5 files changed, 57 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index c258f87..ba96023 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -675,6 +675,40 @@ static void omap3_noncore_dpll_disable(struct clk *clk)
 	_omap3_noncore_dpll_stop(clk);
 }
 
+/**
+ * lookup_dco_sddiv -j-type DPLL4 compensation variables
+ * @clk: pointer to a DPLL struct clk
+ * @dco: digital control oscillator selector
+ * @sd_div: target sigma-delta divider
+ * @m: DPLL multiplier to set
+ * @n: DPLL divider to set
+ */
+void lookup_dco_sddiv(struct clk *clk, u8 *dco, u8 *sd_div, u16 m, u8 n)
+{
+	unsigned long fint, clkinp, sd; /* watch out for overflow */
+	int mod1, mod2;
+	++n; /* always n+1 below */
+	clkinp = clk->parent->rate;
+	fint = (clkinp / n) * m;
+
+	if (fint < 1000000000)
+		*dco = 2;
+	else
+		*dco = 4;
+	/*
+	* target sigma-delta to near 250MHz
+	* sd = ceil[(m/(n+1)) * (clkinp_MHz / 250)]
+	*/
+	clkinp /= 100000; /* shift from MHz to 10*Hz for 38.4 and 19.2*/
+	mod1 = (clkinp * m) % (250 * n);
+	sd = (clkinp * m) / (250 * n);
+	mod2 = sd % 10;
+	sd /= 10;
+
+	if (mod1 + mod2)
+		++sd;
+	*sd_div = sd;
+}
 
 /* Non-CORE DPLL rate set code */
 
@@ -707,6 +741,13 @@ static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
 	v &= ~(dd->mult_mask | dd->div1_mask);
 	v |= m << __ffs(dd->mult_mask);
 	v |= (n - 1) << __ffs(dd->div1_mask);
+	if (dd->jtype) {
+		u8 dco, sd_div;
+		lookup_dco_sddiv(clk, &dco, &sd_div, m, n);
+		v &= ~(dd->dco_sel_mask | dd->sd_div_mask);
+		v |=  dco << __ffs(dd->dco_sel_mask);
+		v |=  sd_div << __ffs(dd->sd_div_mask);
+	}
 	__raw_writel(v, dd->mult_div1_reg);
 
 	/* We let the clock framework set the other output dividers later */
@@ -1022,7 +1063,7 @@ static unsigned long omap3_clkoutx2_recalc(struct clk *clk)
 
 	v = __raw_readl(dd->control_reg) & dd->enable_mask;
 	v >>= __ffs(dd->enable_mask);
-	if (v != OMAP3XXX_EN_DPLL_LOCKED)
+	if (v != OMAP3XXX_EN_DPLL_LOCKED && (!dd->jtype))
 		rate = clk->parent->rate;
 	else
 		rate = clk->parent->rate * 2;
@@ -1135,6 +1176,8 @@ int __init omap2_clk_init(void)
 			cpu_mask |= RATE_IN_3430ES2;
 			cpu_clkflg |= CK_3430ES2;
 		}
+		if (omap3_has_jtype_dpll4())
+			dpll4_ck.dpll_data->jtype = 1;
 	}
 
 	clk_init(&omap2_clk_functions);
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index 6923deb..6f2802b 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -516,9 +516,13 @@
 
 /* CM_CLKSEL2_PLL */
 #define OMAP3430_PERIPH_DPLL_MULT_SHIFT			8
-#define OMAP3430_PERIPH_DPLL_MULT_MASK			(0x7ff << 8)
+#define OMAP3430_PERIPH_DPLL_MULT_MASK			(0xfff << 8)
 #define OMAP3430_PERIPH_DPLL_DIV_SHIFT			0
 #define OMAP3430_PERIPH_DPLL_DIV_MASK			(0x7f << 0)
+#define OMAP3630_PERIPH_DPLL_DCO_SEL_SHIFT		21
+#define OMAP3630_PERIPH_DPLL_DCO_SEL_MASK		(0x7 << 21)
+#define OMAP3630_PERIPH_DPLL_SD_DIV_SHIFT		24
+#define OMAP3630_PERIPH_DPLL_SD_DIV_MASK		(0xff << 24)
 
 /* CM_CLKSEL3_PLL */
 #define OMAP3430_DIV_96M_SHIFT				0
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 702d3b4..9cddddc 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -176,6 +176,8 @@ void __init omap3_check_features(void)
 	OMAP3_CHECK_FEATURE(status, NEON);
 	OMAP3_CHECK_FEATURE(status, ISP);
 
+	if (cpu_is_omap3630())
+		omap3_features |= OMAP3_HAS_JTYPE_DPLL4;
 	/*
 	 * TODO: Get additional info (where applicable)
 	 *       e.g. Size of L2 cache.
@@ -314,6 +316,7 @@ void __init omap3_cpuinfo(void)
 	OMAP3_SHOW_FEATURE(sgx);
 	OMAP3_SHOW_FEATURE(neon);
 	OMAP3_SHOW_FEATURE(isp);
+	OMAP3_SHOW_FEATURE(jtype_dpll4);
 }
 
 /*
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 4b8b0d6..66648d4 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -60,6 +60,9 @@ struct dpll_data {
 	void __iomem		*idlest_reg;
 	u32			autoidle_mask;
 	u32			freqsel_mask;
+	u32			dco_sel_mask;
+	u32			sd_div_mask;
+	u8			jtype;
 	u32			idlest_mask;
 	u8			auto_recal_bit;
 	u8			recal_en_bit;
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 7cb0556..6201a2e 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -482,6 +482,7 @@ extern u32 omap3_features;
 #define OMAP3_HAS_SGX			BIT(2)
 #define OMAP3_HAS_NEON			BIT(3)
 #define OMAP3_HAS_ISP			BIT(4)
+#define OMAP3_HAS_JTYPE_DPLL4		BIT(5)
 
 #define OMAP3_HAS_FEATURE(feat,flag)			\
 static inline unsigned int omap3_has_ ##feat(void)	\
@@ -494,5 +495,6 @@ OMAP3_HAS_FEATURE(sgx, SGX)
 OMAP3_HAS_FEATURE(iva, IVA)
 OMAP3_HAS_FEATURE(neon, NEON)
 OMAP3_HAS_FEATURE(isp, ISP)
+OMAP3_HAS_FEATURE(jtype_dpll4, JTYPE_DPLL4)
 
 #endif
-- 
1.6.3.3


^ permalink raw reply related	[flat|nested] 8+ messages in thread

* RE: [PATCH 2/2] OMAP3:clk: introduce DPLL4 jtype support
  2009-10-20 10:48   ` [PATCH 2/2] OMAP3:clk: introduce DPLL4 jtype support Nishanth Menon
@ 2009-10-20 14:15     ` Aguirre Rodriguez, Sergio Alberto
  2009-10-20 14:47       ` Woodruff, Richard
  0 siblings, 1 reply; 8+ messages in thread
From: Aguirre Rodriguez, Sergio Alberto @ 2009-10-20 14:15 UTC (permalink / raw)
  To: Menon, Nishanth, linux-omap
  Cc: Woodruff, Richard, Pandita, Vikram, Sonasath, Moiz

Nishanth, 

From: linux-omap-owner@vger.kernel.org 
[mailto:linux-omap-owner@vger.kernel.org] On Behalf Of Menon, Nishanth
Sent: Tuesday, October 20, 2009 5:49 AM
> From: Richard Woodruff <r-woodruff2@ti.com>
> 
> DPLL4 for 3630 introduces a changed block requiring
> special divisor bits and additional reg fields
> 
> To allow for silicons to use this, this is introduced
> as a omap3_has_jtype_dpll4() and is enabled for 3630
> silicon
> 
> Tested with SDP3430, SDP3630
> 
> Cc: Vikram Pandita <vikram.pandita@ti.com>
> Cc: Sonasath, Moiz Sonasath <m-sonasath@ti.com>
> Signed-off-by: Richard Woodruff <r-woodruff2@ti.com>
> Signed-off-by: Nishanth Menon <nm@ti.com>
> ---
>  arch/arm/mach-omap2/clock34xx.c         |   45 
> ++++++++++++++++++++++++++++++-
>  arch/arm/mach-omap2/cm-regbits-34xx.h   |    6 +++-
>  arch/arm/mach-omap2/id.c                |    3 ++
>  arch/arm/plat-omap/include/plat/clock.h |    3 ++
>  arch/arm/plat-omap/include/plat/cpu.h   |    2 +
>  5 files changed, 57 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/clock34xx.c 
> b/arch/arm/mach-omap2/clock34xx.c
> index c258f87..ba96023 100644
> --- a/arch/arm/mach-omap2/clock34xx.c
> +++ b/arch/arm/mach-omap2/clock34xx.c
> @@ -675,6 +675,40 @@ static void 
> omap3_noncore_dpll_disable(struct clk *clk)
>  	_omap3_noncore_dpll_stop(clk);
>  }
>  
> +/**
> + * lookup_dco_sddiv -j-type DPLL4 compensation variables

Put a space before the j-type, and add better description.
Doesn't clarify what it really does IMHO:

Something like:
"* lookup_dco_sddiv - Set j-type DPLL4 compensation variables"

> + * @clk: pointer to a DPLL struct clk
> + * @dco: digital control oscillator selector
> + * @sd_div: target sigma-delta divider
> + * @m: DPLL multiplier to set
> + * @n: DPLL divider to set
> + */
> +void lookup_dco_sddiv(struct clk *clk, u8 *dco, u8 *sd_div, 
> u16 m, u8 n)
> +{
> +	unsigned long fint, clkinp, sd; /* watch out for overflow */
> +	int mod1, mod2;

Add Space after var declarations.

Declare function as static.

Should you do something like:

	BUG_ON(!clk->parent);

? (not sure)

What do you think?

Regards,
Sergio

> +	++n; /* always n+1 below */
> +	clkinp = clk->parent->rate;
> +	fint = (clkinp / n) * m;
> +
> +	if (fint < 1000000000)
> +		*dco = 2;
> +	else
> +		*dco = 4;
> +	/*
> +	* target sigma-delta to near 250MHz
> +	* sd = ceil[(m/(n+1)) * (clkinp_MHz / 250)]
> +	*/
> +	clkinp /= 100000; /* shift from MHz to 10*Hz for 38.4 and 19.2*/
> +	mod1 = (clkinp * m) % (250 * n);
> +	sd = (clkinp * m) / (250 * n);
> +	mod2 = sd % 10;
> +	sd /= 10;
> +
> +	if (mod1 + mod2)
> +		++sd;
> +	*sd_div = sd;
> +}
>  
>  /* Non-CORE DPLL rate set code */
>  
> @@ -707,6 +741,13 @@ static int 
> omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
>  	v &= ~(dd->mult_mask | dd->div1_mask);
>  	v |= m << __ffs(dd->mult_mask);
>  	v |= (n - 1) << __ffs(dd->div1_mask);
> +	if (dd->jtype) {
> +		u8 dco, sd_div;
> +		lookup_dco_sddiv(clk, &dco, &sd_div, m, n);
> +		v &= ~(dd->dco_sel_mask | dd->sd_div_mask);
> +		v |=  dco << __ffs(dd->dco_sel_mask);
> +		v |=  sd_div << __ffs(dd->sd_div_mask);
> +	}
>  	__raw_writel(v, dd->mult_div1_reg);
>  
>  	/* We let the clock framework set the other output 
> dividers later */
> @@ -1022,7 +1063,7 @@ static unsigned long 
> omap3_clkoutx2_recalc(struct clk *clk)
>  
>  	v = __raw_readl(dd->control_reg) & dd->enable_mask;
>  	v >>= __ffs(dd->enable_mask);
> -	if (v != OMAP3XXX_EN_DPLL_LOCKED)
> +	if (v != OMAP3XXX_EN_DPLL_LOCKED && (!dd->jtype))
>  		rate = clk->parent->rate;
>  	else
>  		rate = clk->parent->rate * 2;
> @@ -1135,6 +1176,8 @@ int __init omap2_clk_init(void)
>  			cpu_mask |= RATE_IN_3430ES2;
>  			cpu_clkflg |= CK_3430ES2;
>  		}
> +		if (omap3_has_jtype_dpll4())
> +			dpll4_ck.dpll_data->jtype = 1;
>  	}
>  
>  	clk_init(&omap2_clk_functions);
> diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h 
> b/arch/arm/mach-omap2/cm-regbits-34xx.h
> index 6923deb..6f2802b 100644
> --- a/arch/arm/mach-omap2/cm-regbits-34xx.h
> +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
> @@ -516,9 +516,13 @@
>  
>  /* CM_CLKSEL2_PLL */
>  #define OMAP3430_PERIPH_DPLL_MULT_SHIFT			8
> -#define OMAP3430_PERIPH_DPLL_MULT_MASK			
> (0x7ff << 8)
> +#define OMAP3430_PERIPH_DPLL_MULT_MASK			
> (0xfff << 8)
>  #define OMAP3430_PERIPH_DPLL_DIV_SHIFT			0
>  #define OMAP3430_PERIPH_DPLL_DIV_MASK			
> (0x7f << 0)
> +#define OMAP3630_PERIPH_DPLL_DCO_SEL_SHIFT		21
> +#define OMAP3630_PERIPH_DPLL_DCO_SEL_MASK		(0x7 << 21)
> +#define OMAP3630_PERIPH_DPLL_SD_DIV_SHIFT		24
> +#define OMAP3630_PERIPH_DPLL_SD_DIV_MASK		(0xff << 24)
>  
>  /* CM_CLKSEL3_PLL */
>  #define OMAP3430_DIV_96M_SHIFT				0
> diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
> index 702d3b4..9cddddc 100644
> --- a/arch/arm/mach-omap2/id.c
> +++ b/arch/arm/mach-omap2/id.c
> @@ -176,6 +176,8 @@ void __init omap3_check_features(void)
>  	OMAP3_CHECK_FEATURE(status, NEON);
>  	OMAP3_CHECK_FEATURE(status, ISP);
>  
> +	if (cpu_is_omap3630())
> +		omap3_features |= OMAP3_HAS_JTYPE_DPLL4;
>  	/*
>  	 * TODO: Get additional info (where applicable)
>  	 *       e.g. Size of L2 cache.
> @@ -314,6 +316,7 @@ void __init omap3_cpuinfo(void)
>  	OMAP3_SHOW_FEATURE(sgx);
>  	OMAP3_SHOW_FEATURE(neon);
>  	OMAP3_SHOW_FEATURE(isp);
> +	OMAP3_SHOW_FEATURE(jtype_dpll4);
>  }
>  
>  /*
> diff --git a/arch/arm/plat-omap/include/plat/clock.h 
> b/arch/arm/plat-omap/include/plat/clock.h
> index 4b8b0d6..66648d4 100644
> --- a/arch/arm/plat-omap/include/plat/clock.h
> +++ b/arch/arm/plat-omap/include/plat/clock.h
> @@ -60,6 +60,9 @@ struct dpll_data {
>  	void __iomem		*idlest_reg;
>  	u32			autoidle_mask;
>  	u32			freqsel_mask;
> +	u32			dco_sel_mask;
> +	u32			sd_div_mask;
> +	u8			jtype;
>  	u32			idlest_mask;
>  	u8			auto_recal_bit;
>  	u8			recal_en_bit;
> diff --git a/arch/arm/plat-omap/include/plat/cpu.h 
> b/arch/arm/plat-omap/include/plat/cpu.h
> index 7cb0556..6201a2e 100644
> --- a/arch/arm/plat-omap/include/plat/cpu.h
> +++ b/arch/arm/plat-omap/include/plat/cpu.h
> @@ -482,6 +482,7 @@ extern u32 omap3_features;
>  #define OMAP3_HAS_SGX			BIT(2)
>  #define OMAP3_HAS_NEON			BIT(3)
>  #define OMAP3_HAS_ISP			BIT(4)
> +#define OMAP3_HAS_JTYPE_DPLL4		BIT(5)
>  
>  #define OMAP3_HAS_FEATURE(feat,flag)			\
>  static inline unsigned int omap3_has_ ##feat(void)	\
> @@ -494,5 +495,6 @@ OMAP3_HAS_FEATURE(sgx, SGX)
>  OMAP3_HAS_FEATURE(iva, IVA)
>  OMAP3_HAS_FEATURE(neon, NEON)
>  OMAP3_HAS_FEATURE(isp, ISP)
> +OMAP3_HAS_FEATURE(jtype_dpll4, JTYPE_DPLL4)
>  
>  #endif
> -- 
> 1.6.3.3
> 
> --
> To unsubscribe from this list: send the line "unsubscribe 
> linux-omap" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 
> 

^ permalink raw reply	[flat|nested] 8+ messages in thread

* RE: [PATCH 2/2] OMAP3:clk: introduce DPLL4 jtype support
  2009-10-20 14:15     ` Aguirre Rodriguez, Sergio Alberto
@ 2009-10-20 14:47       ` Woodruff, Richard
  2009-10-20 14:50         ` Menon, Nishanth
  0 siblings, 1 reply; 8+ messages in thread
From: Woodruff, Richard @ 2009-10-20 14:47 UTC (permalink / raw)
  To: Aguirre Rodriguez, Sergio Alberto, Menon, Nishanth, linux-omap
  Cc: Pandita, Vikram, Sonasath, Moiz


> From: Aguirre Rodriguez, Sergio Alberto
> Sent: Tuesday, October 20, 2009 9:16 AM

> > + * lookup_dco_sddiv -j-type DPLL4 compensation variables
>
> Put a space before the j-type, and add better description.
> Doesn't clarify what it really does IMHO:
>
> Something like:
> "* lookup_dco_sddiv - Set j-type DPLL4 compensation variables"

For 45nm it was necessary to use a different DPLL IP for DPLL4 (dpllj).  The other DPLLs are same which was used in 65nm (dpllm).  The register interface is slightly different.

Code could have said is type A or B, but simple choice was to follow internal name convention.

Regards,
Richard W.

^ permalink raw reply	[flat|nested] 8+ messages in thread

* RE: [PATCH 2/2] OMAP3:clk: introduce DPLL4 jtype support
  2009-10-20 14:47       ` Woodruff, Richard
@ 2009-10-20 14:50         ` Menon, Nishanth
  0 siblings, 0 replies; 8+ messages in thread
From: Menon, Nishanth @ 2009-10-20 14:50 UTC (permalink / raw)
  To: Woodruff, Richard, Aguirre Rodriguez, Sergio Alberto, linux-omap
  Cc: Pandita, Vikram, Sonasath, Moiz

> From: Woodruff, Richard
> Sent: Tuesday, October 20, 2009 9:48 AM
> 
> 
> > From: Aguirre Rodriguez, Sergio Alberto
> > Sent: Tuesday, October 20, 2009 9:16 AM
> 
> > > + * lookup_dco_sddiv -j-type DPLL4 compensation variables
> >
> > Put a space before the j-type, and add better description.
> > Doesn't clarify what it really does IMHO:
> >
> > Something like:
> > "* lookup_dco_sddiv - Set j-type DPLL4 compensation variables"
> 
> For 45nm it was necessary to use a different DPLL IP for DPLL4 (dpllj).
> The other DPLLs are same which was used in 65nm (dpllm).  The register
> interface is slightly different.
> 
> Code could have said is type A or B, but simple choice was to follow
> internal name convention.
> 
Any comments on a neat handling of condition where clk->parent is NULL? A BUG_ON(!clk->parent) is good?

Regards,
Nishanth Menon

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCH 1/2] OMAP3: move check_revision above check_features
  2009-10-20 10:48 ` [PATCH 1/2] OMAP3: move check_revision above check_features Nishanth Menon
  2009-10-20 10:48   ` [PATCH 2/2] OMAP3:clk: introduce DPLL4 jtype support Nishanth Menon
@ 2009-11-03 13:54   ` Mika Westerberg
  2009-11-12 21:14   ` [APPLIED] " Tony Lindgren
  2 siblings, 0 replies; 8+ messages in thread
From: Mika Westerberg @ 2009-11-03 13:54 UTC (permalink / raw)
  To: Nishanth Menon; +Cc: linux-omap

On Tue, Oct 20, 2009 at 05:48:57AM -0500, Nishanth Menon wrote:
> omap3_check_revision() does not depend on omap3_check_features()
> move this above so that we can add logic based on revision
> detected in check_features.
> 
> Signed-off-by: Nishanth Menon <nm@ti.com>

Acked-by: Mika Westerberg <mika.westerberg@iki.fi>

Br,
MW

^ permalink raw reply	[flat|nested] 8+ messages in thread

* [APPLIED] [PATCH 1/2] OMAP3: move check_revision above check_features
  2009-10-20 10:48 ` [PATCH 1/2] OMAP3: move check_revision above check_features Nishanth Menon
  2009-10-20 10:48   ` [PATCH 2/2] OMAP3:clk: introduce DPLL4 jtype support Nishanth Menon
  2009-11-03 13:54   ` [PATCH 1/2] OMAP3: move check_revision above check_features Mika Westerberg
@ 2009-11-12 21:14   ` Tony Lindgren
  2 siblings, 0 replies; 8+ messages in thread
From: Tony Lindgren @ 2009-11-12 21:14 UTC (permalink / raw)
  To: linux-omap

This patch has been applied to the linux-omap
by youw fwiendly patch wobot.

Branch in linux-omap: for-next

Initial commit ID (Likely to change): fbb9e29aa28c779f48c9af03988c602e2ed7c5bb

PatchWorks
http://patchwork.kernel.org/patch/54925/

Git (Likely to change, and takes a while to get mirrored)
http://git.kernel.org/?p=linux/kernel/git/tmlind/linux-omap-2.6.git;a=commit;h=fbb9e29aa28c779f48c9af03988c602e2ed7c5bb



^ permalink raw reply	[flat|nested] 8+ messages in thread

end of thread, other threads:[~2009-11-12 21:14 UTC | newest]

Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2009-10-20 10:48 [PATCH 0/2] OMAP3: introduce DPLL4 Jtype Nishanth Menon
2009-10-20 10:48 ` [PATCH 1/2] OMAP3: move check_revision above check_features Nishanth Menon
2009-10-20 10:48   ` [PATCH 2/2] OMAP3:clk: introduce DPLL4 jtype support Nishanth Menon
2009-10-20 14:15     ` Aguirre Rodriguez, Sergio Alberto
2009-10-20 14:47       ` Woodruff, Richard
2009-10-20 14:50         ` Menon, Nishanth
2009-11-03 13:54   ` [PATCH 1/2] OMAP3: move check_revision above check_features Mika Westerberg
2009-11-12 21:14   ` [APPLIED] " Tony Lindgren

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