From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from midgard.sc.steeleye.com (midgard.sc.steeleye.com [172.17.6.40]) by hancock.sc.steeleye.com (8.11.6/linuxconf) with ESMTP id i3UGPla08568; Fri, 30 Apr 2004 12:25:47 -0400 From: James Bottomley To: PARISC list In-Reply-To: <20040430162037.9D2B94945CD@palinux.hppa> References: <20040430162037.9D2B94945CD@palinux.hppa> Content-Type: text/plain Date: 30 Apr 2004 11:25:46 -0500 Message-Id: <1083342347.2063.38.camel@mulgrave> Mime-Version: 1.0 Cc: parisc-linux-cvs@lists.parisc-linux.org Subject: [parisc-linux] Re: [parisc-linux-cvs] linux-2.6 jejb List-Id: parisc-linux developers list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , On Fri, 2004-04-30 at 11:20, James Bottomley wrote: > CVSROOT: /var/cvs > Module name: linux-2.6 > Changes by: jejb 04/04/30 10:20:37 > > Modified files: > . : Makefile > arch/parisc/kernel: asm-offsets.c entry.S init_task.c > include/asm-parisc: page.h pgalloc.h pgtable.h > > Log message: > Update the parametrisation of our page tables > > This fix also allows variable size pgd and pmd and thus lays the ground > work for expanding the number of page table flags we have ===== arch/parisc/kernel/asm-offsets.c 1.6 vs edited ===== --- 1.6/arch/parisc/kernel/asm-offsets.c Sun Apr 25 04:00:10 2004 +++ edited/arch/parisc/kernel/asm-offsets.c Thu Apr 29 12:52:22 2004 @@ -276,6 +276,12 @@ BLANK(); DEFINE(PA_BLOCKSTEP_BIT, 31-PT_BLOCKSTEP_BIT); DEFINE(PA_SINGLESTEP_BIT, 31-PT_SINGLESTEP_BIT); + BLANK(); + DEFINE(ASM_PMD_SHIFT, PMD_SHIFT); + DEFINE(ASM_PGDIR_SHIFT, PGDIR_SHIFT); + DEFINE(ASM_BITS_PER_PGD, BITS_PER_PGD); + DEFINE(ASM_BITS_PER_PMD, BITS_PER_PMD); + DEFINE(ASM_BITS_PER_PTE, BITS_PER_PTE); DEFINE(ASM_PMD_ENTRY, ((__PAGE_OFFSET & PMD_MASK) >> PMD_SHIFT)); BLANK(); return 0; ===== arch/parisc/kernel/entry.S 1.17 vs edited ===== --- 1.17/arch/parisc/kernel/entry.S Tue Apr 27 06:20:11 2004 +++ edited/arch/parisc/kernel/entry.S Thu Apr 29 18:16:28 2004 @@ -455,21 +455,25 @@ /* Look up a PTE in a 2-Level scheme (faulting at each * level if the entry isn't present */ .macro L2_ptep pmd,pte,index,va,fault - EXTR \va,31-PMD_SHIFT,PAGE_SHIFT-BITS_PER_PMD,\index +#if PT_NLEVELS == 3 + EXTR \va,31-ASM_PMD_SHIFT,ASM_BITS_PER_PMD,\index +#else + EXTR \va,31-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index +#endif copy %r0,\pte DEP %r0,31,PAGE_SHIFT,\pmd /* clear offset */ LDREG,s \index(\pmd),\pmd - EXTR \va,31-PAGE_SHIFT,PAGE_SHIFT-BITS_PER_PTE,\index + EXTR \va,31-PAGE_SHIFT,ASM_BITS_PER_PTE,\index bb,>=,n \pmd,_PAGE_PRESENT_BIT,\fault DEP %r0,31,PAGE_SHIFT,\pmd /* clear offset */ - shladd \index,BITS_PER_PTE,\pmd,\pmd + shladd \index,BITS_PER_PTE_ENTRY,\pmd,\pmd LDREG %r0(\pmd),\pte /* pmd is now pte */ bb,>=,n \pte,_PAGE_PRESENT_BIT,\fault .endm /* Look up PTE in a 3-Level scheme */ .macro L3_ptep pgd,pte,index,va,fault - extrd,u \va,63-PGDIR_SHIFT,PAGE_SHIFT-BITS_PER_PGD,\index + extrd,u \va,63-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index copy %r0,\pte ldd,s \index(\pgd),\pgd bb,>=,n \pgd,_PAGE_PRESENT_BIT,\fault ===== arch/parisc/kernel/init_task.c 1.7 vs edited ===== --- 1.7/arch/parisc/kernel/init_task.c Tue Feb 3 23:41:56 2004 +++ edited/arch/parisc/kernel/init_task.c Thu Apr 29 11:42:08 2004 @@ -52,7 +52,7 @@ __attribute__((aligned(128))) __attribute__((__section__(".data.init_task"))) = { INIT_THREAD_INFO(init_task) }; -pgd_t swapper_pg_dir[PTRS_PER_PGD] __attribute__ ((aligned(4096))) = { {0}, }; +pgd_t swapper_pg_dir[PTRS_PER_PGD] __attribute__ ((aligned(PAGE_SIZE<>PMD_SHIFT) & (PTRS_PER_PMD-1))) #else