From: Grant Grundler <grundler@cup.hp.com>
To: "Gunneswara Marripudi" <raomg@cup.hp.com>
Cc: parisc-linux@puffin.external.hp.com
Subject: Re: Question on Linux DMA routines
Date: Thu, 30 Nov 2000 10:01:13 -0800 [thread overview]
Message-ID: <200011301801.KAA29413@milano.cup.hp.com> (raw)
In-Reply-To: Your message of "Thu, 30 Nov 2000 09:31:14 PST." <200011301731.JAA29335@milano.cup.hp.com>
Grant Grundler wrote:
...
> The HW *is* fully coherent when the CPU doesn't cache the pages.
> Only systems with PCX-L/L2 CPU (need to) operate this way.
> All other platforms have an I/O MMU which manages the coherency.
Correction - PCX-T and older platforms are not coherent and U-bit
isn't available/useable on those machines. Drivers must do their own
cache flushing. sim700 (LASI SCSI) does this and I think Apricot
(LASI LAN) too. I'm suspecting this might be part of the 735 problems.
grant
Grant Grundler
Unix Systems Enablement Lab
+1.408.447.7253
next prev parent reply other threads:[~2000-11-30 17:59 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <01c05aac$657dec80$0f0d8421@hpinddm>
2000-11-30 17:31 ` Question on Linux DMA routines Grant Grundler
2000-11-30 18:01 ` Grant Grundler [this message]
2000-11-30 20:09 ` Richard Hirst
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