Re: [parisc-linux] PA8800/ZX1 support committed to 2.6.7-rc2-pa2

[Grant Grundler <grundler@parisc-linux.org>]

On Sat, Jun 05, 2004 at 04:19:24PM -0500, James Bottomley wrote:
> On Sat, 2004-06-05 at 16:05, Grant Grundler wrote:
> The pa8800 only has a 750k/750k VIPT cache, that's smaller than my
> raven.  The 32M L2 cache is PIPT, which doesn't suffer from aliasing or
> address remapping effects---in fact, the PA engineers probably arranged
> for a fdc not to flush it because there's no point; the only coherency
> problems the PIPT cache has is with I/O, which is supposed to be fully
> coherent in the ZX1, isn't it.

Yes - especially since I haven't attempted to add any special support
for 64-bit cards. The "IOMMU Bypass" mode on ZX1 is worth implementing
for 64-bit cards and I might in fact require it for graphics and
infiniband support.


> Thus, we'd only pick up a caching
> problems like you describe from the VIPT caches.

ok.

> > Any good ideas on how to prove IO is coherent?
> 
> Well, yes, but not without driver magic.  You program a device to take a
> piece of data in and rewrite it to a different buffer, then you compare
> buffers (making sure the first had a pattern in it and the second was
> completely clear).

tg3 driver infact has such a test...let me think about that some more.
I might hack the test to be more exhaustive.

> Well, it could be an I/O coherency problem, but if you have one of
> those, I'm surprised it boots at all.

For that bug, one could occasionally end up with a stale IO TLB entry.
And I'm wondering if that's possible when "swapping in" different
parts of an executable binary. To date, I'm under the impression
only executable pages are seeing this problem.  If it were IO,
I should be seeing it with data too - ie .c file cause errors.
Maybe I just need to exercize it more to make that happen.

thanks,
grant
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