Re: [parisc-linux] Does it lakes some cloberred r1 in

["Michael S. Zick" <mszick@morethan.org>]

On Tue April 25 2006 10:17, Michael S. Zick wrote:
> On Mon April 24 2006 10:35, John David Anglin wrote:
> > > ldcw,co target_address
> > > 
> > > Where target_address includes the magic byte[0] of 
> > > the cache line.
> > 
> > Where is this documented?
> > 
> Close, not quite there yet:
> 
> HP patent number: 4,713,755
> 
> The page to retrieve this by number:
> http://patft1.uspto.gov/netahtml/PTO/srchnum.htm
> 
> Now it should be a 'simple' matter to just read
> every patent that references this one.
> 

One more conjecture confirmed,

The cache lines are a master/slave arrangement,
only one processor (or device) can be the master
(owner) of the cache line.

This is accomplished by keeping the cpu id (address)
of the master in the virtual tag.

Ref: HP patent number: 5,197,146

That is how the logical 'makePrivate' of the formal
memory model happens.

Translation:

Thou shall not allow load balancing to migrate a
task that holds a spinlock - you leave the master
of that cache line on the prior processor.

Mike
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