RE: [parisc-linux] Re: [parisc-linux-cvs] linux carlos

["Joel Soete" <jsoe0708@tiscali.be>]

Hi Jim,

Well come :)
> I haven't really been following this thread, so I don't know what
>problem you're actually trying to solve, but I'd like to point out a few
>aspects of the PA-RISC processor architecture.
>
To be short, the pa linux kernel boot well on A model as SMP (Multiprocessor
mode) but panic on L/N model. And a pb in tlb management is suspected.

>Comments mixed with the original text, below.
>
> -- Jim
>   
>> HP Itanium/PA-RISC Processor Architect

>If you use fdc, fic, or pdc, then they are broadcast to other
>processors, but fdce and fice are not.

Thanks I will check if such a code is used.

>While you can use ldda and stda to access memory using absolute
>(physical) addresses instead of virtual, these instructions do *not*
>bypass the cache.  And because PA processors use virtually-indexed
>caches, the rules for mixing virtual and absolute accesses, and have
>them all remain cache-coherent, are complicated.  If you really need to
>do this, then you'll have to read and understand all of Appendix F, "TLB
>and Cache Control", in the PA-RISC 2.0 Architecture manual (the "Kane"
>book).

Yes, very accurate reference, but imo it is not a course on PA-RISC asm (I
mean, as a beginner, as i am, would like to find with some trial example
showing what is good and trivial errors to not commit).

Thanks for your clear comments,
    Joel


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