On 10/21/2014 10:01 PM, John David Anglin wrote:
> On 10/21/2014 3:46 PM, Helge Deller wrote:
>>   /* LDCW, the only atomic read-write operation PA-RISC has. *sigh*.  */
>> -#define __ldcw(a) ({                        \
>> -    unsigned __ret;                        \
>> -    __asm__ __volatile__(__LDCW " 0(%2),%0"            \
>> -        : "=r" (__ret), "+m" (*(a)) : "r" (a));        \
>> -    __ret;                            \
>> -})
>> +static inline unsigned int __ldcw(volatile unsigned int *address)
>> +{
>> +    unsigned int ret;
>> +    register volatile unsigned int *a = address;
>> +    __asm__ __volatile__(__LDCW " 0(%2),%0"
>> +        : "=r" (ret), "+m" (*(a)) : "r" (a));
>> +    return ret;
>> +}
> You could keep the old macro version for 32-bit builds as the problem shouldn't occur there.

Attached is an updated patch/work-around which just reuses the existing register.
I don't like this patch much, but it's better than nothing for now.

Helge