From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EEF24C77B73 for ; Thu, 20 Apr 2023 11:21:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233838AbjDTLVV (ORCPT ); Thu, 20 Apr 2023 07:21:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47364 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235070AbjDTLUs (ORCPT ); Thu, 20 Apr 2023 07:20:48 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7C604B46C; Thu, 20 Apr 2023 04:18:52 -0700 (PDT) From: Thomas Gleixner DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1681989462; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=t5XqcHn966UpzdXXi00/lSAzdYJUEVQOjSwT6u3WS8Y=; b=pAb6n5DzMyj9cPuaDVh1nEa4eMPTGWjlabRanF0gKYgC9Dt16bSxIF65k8A6Phxdd7b+m1 8rtjGcomkGZGHPfqi5gCMDsNgIxkIz7fE3iWI1yVPEr7CzAxuLO52VMUjueL9yA1cignQ0 2aZBXvrGK95/A3SZLIzR4CO2Gt6BjAJeGZFwZ0r5DeQJZY9f+42NHleeHSDTjxF+sNMncp Pj8zsu3xSjO1U4uiCaq79l7sMSO/XzBLws+gTsKxCyOwMVcTz52DRxt/Fl9qBPDScBZpAE EzRwxWNG9FQP9wQGTFVsN5ZBm94BxGBjsCTcRwuXnpgNipezItO8FzlRvwCjfQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1681989462; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=t5XqcHn966UpzdXXi00/lSAzdYJUEVQOjSwT6u3WS8Y=; b=K7n7gkxobQSbdvGZErkz25VRgfZFGdff1cfdZxrOPRjWpL/QdasoOCujc47S1yFH9hOfDu jdhNH58O+gxzlPDw== To: Andrew Cooper , Paul Menzel Cc: linux-kernel@vger.kernel.org, x86@kernel.org, David Woodhouse , Brian Gerst , Arjan van de Veen , Paolo Bonzini , Paul McKenney , Tom Lendacky , Sean Christopherson , Oleksandr Natalenko , "Guilherme G. Piccoli" , Piotr Gorski , David Woodhouse , Usama Arif , =?utf-8?B?SsO8cmdlbiBHcm/Dnw==?= , Boris Ostrovsky , xen-devel@lists.xenproject.org, Russell King , Arnd Bergmann , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Will Deacon , Guo Ren , linux-csky@vger.kernel.org, Thomas Bogendoerfer , linux-mips@vger.kernel.org, "James E. J. Bottomley" , Helge Deller , linux-parisc@vger.kernel.org, Paul Walmsley , Palmer Dabbelt , linux-riscv@lists.infradead.org, Mark Rutland , Sabin Rapan Subject: Re: [patch 00/37] cpu/hotplug, x86: Reworked parallel CPU bringup In-Reply-To: <26d385da-2ede-5d73-2959-84c8f7d89e03@citrix.com> References: <20230414225551.858160935@linutronix.de> <8247ce4d-15b7-03b2-0c9b-74f8cd6cad50@molgen.mpg.de> <87wn2a4la5.ffs@tglx> <87ttxd4qxz.ffs@tglx> <87r0sh4m7a.ffs@tglx> <8592a301-9933-1cad-bd61-8d97e7c7493b@molgen.mpg.de> <87a5z443g2.ffs@tglx> <877cu83v45.ffs@tglx> <874jpc3s3r.ffs@tglx> <0f5463fd-9c4a-6361-adbb-dd89dbb9138d@citrix.com> <871qkf3qek.ffs@tglx> <26d385da-2ede-5d73-2959-84c8f7d89e03@citrix.com> Date: Thu, 20 Apr 2023 13:17:40 +0200 Message-ID: <87y1mm3iqz.ffs@tglx> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-parisc@vger.kernel.org On Thu, Apr 20 2023 at 10:23, Andrew Cooper wrote: > On 20/04/2023 9:32 am, Thomas Gleixner wrote: >> I'm pondering to simply deny parallel mode if x2APIC is not there. > > I'm not sure if that will help much. Spoilsport. > Just because x2APIC is there doesn't mean it's in use.=C2=A0 There are > several generations of Intel system which have x2APIC but also use the > opt-out bit in ACPI tables.=C2=A0 There are some machines which have > mismatched APIC-ness settings in the BIOS->OS handover. > > There's very little you can do on the BSP alone to know for certain that > the APs come out of wait-for-SIPI already in x2APIC mode. Yeah. Reading the APIC that early is going to be entertaining too :) > One way is the =C3=86PIC Leak "locked into x2APIC mode" giant security > bodge.=C2=A0 Bah. > If the system really does have a CPU with an APIC ID above 0xfe, then > chances are good that the APs come out consistently... Anything else would be really magic :)