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[103.168.172.201]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-88c6089a7c3sm13752156d6.27.2025.12.18.01.18.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Dec 2025 01:18:20 -0800 (PST) Received: from phl-compute-03.internal (phl-compute-03.internal [10.202.2.43]) by mailfauth.phl.internal (Postfix) with ESMTP id 93062F4007D; Thu, 18 Dec 2025 04:18:19 -0500 (EST) Received: from phl-frontend-03 ([10.202.2.162]) by phl-compute-03.internal (MEProxy); Thu, 18 Dec 2025 04:18:19 -0500 X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeefgedrtddtgdeghedtgecutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpuffrtefokffrpgfnqfghnecuuegr ihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenucfjug hrpeffhffvvefukfhfgggtuggjsehttdertddttddvnecuhfhrohhmpeeuohhquhhnucfh vghnghcuoegsohhquhhnrdhfvghnghesghhmrghilhdrtghomheqnecuggftrfgrthhtvg hrnhephedugfduffffteeutddvheeuveelvdfhleelieevtdeguefhgeeuveeiudffiedv necuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrhhomhepsghoqh hunhdomhgvshhmthhprghuthhhphgvrhhsohhnrghlihhthidqieelvdeghedtieegqddu jeejkeehheehvddqsghoqhhunhdrfhgvnhhgpeepghhmrghilhdrtghomhesfhhigihmvg drnhgrmhgvpdhnsggprhgtphhtthhopedviedpmhhouggvpehsmhhtphhouhhtpdhrtghp thhtohepfhhujhhithgrrdhtohhmohhnohhrihesghhmrghilhdrtghomhdprhgtphhtth hopehojhgvuggrsehkvghrnhgvlhdrohhrghdprhgtphhtthhopehpvghtvghriiesihhn fhhrrgguvggrugdrohhrghdprhgtphhtthhopeifihhllheskhgvrhhnvghlrdhorhhgpd hrtghpthhtoheprggtohhurhgsohhtsehnvhhiughirgdrtghomhdprhgtphhtthhopegr rdhhihhnuggsohhrgheskhgvrhhnvghlrdhorhhgpdhrtghpthhtoheprghlihgtvghrhi hhlhesghhoohhglhgvrdgtohhmpdhrtghpthhtohepsghjohhrnhefpghghhesphhrohht ohhnmhgrihhlrdgtohhmpdhrtghpthhtohepuggrkhhrsehkvghrnhgvlhdrohhrgh X-ME-Proxy: Feedback-ID: iad51458e:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Thu, 18 Dec 2025 04:18:18 -0500 (EST) Date: Thu, 18 Dec 2025 18:18:17 +0900 From: Boqun Feng To: FUJITA Tomonori Cc: ojeda@kernel.org, peterz@infradead.org, will@kernel.org, acourbot@nvidia.com, a.hindborg@kernel.org, aliceryhl@google.com, bjorn3_gh@protonmail.com, dakr@kernel.org, gary@garyguo.net, lossin@kernel.org, mark.rutland@arm.com, tmgross@umich.edu, rust-for-linux@vger.kernel.org, "James E.J. Bottomley" , Helge Deller , linux-parisc@vger.kernel.org, "David S. Miller" , Andreas Larsson , sparclinux@vger.kernel.org, Vineet Gupta , linux-snps-arc@lists.infradead.org, Brian Cain , linux-hexagon@vger.kernel.org, linux-arch@vger.kernel.org Subject: Re: [PATCH v1 0/4] rust: Add i8/i16 atomic xchg helpers Message-ID: References: <20251217213742.639812-1-fujita.tomonori@gmail.com> Precedence: bulk X-Mailing-List: linux-parisc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20251217213742.639812-1-fujita.tomonori@gmail.com> [Cc parisc, sparc32, arc and hexagon] On Thu, Dec 18, 2025 at 06:37:38AM +0900, FUJITA Tomonori wrote: > This adds atomic xchg helpers with full, acquire, release, and relaxed > orderings in preparation for i8/i16 atomic xchg support. > > The architectures supporting Rust, implement atomic xchg families > using architecture-specific instructions. So the helpers just call > them. > > Note that the architectures that support Rust handle xchg differently: > > - arm64 and riscv support xchg with all the orderings. > > - x86_64 and loongarch support only full-ordering xchg. They calls the > full-ordering xchg for any orderings. > > - arm v7 supports only relaxed-odering xchg. It uses __atomic_op_ > macros to add barriers properly. > Thanks for the work! And please do Cc linux-arch next time when doing architecture-related changes. We would get more experts to take a look. I think the current implementation expects that xchg() work with normal store/load, and that requires ARCH_SUPPORTS_ATOMIC_RMW. So could you add a comment saying the current implementation only support ARCH_SUPPORTS_ATOMIC_RMW architectures? And when you wire up the rust helpers, I think using #[cfg(CONFIG_ARCH_SUPPORTS_ATOMIC_RMW)] is a good idea. This will at least let the !ARCH_SUPPORTS_ATOMIC_RMW archs know that something is missing here. Regards, Boqun > FUJITA Tomonori (4): > rust: helpers: Add i8/i16 atomic xchg helpers > rust: helpers: Add i8/i16 atomic xchg_acquire helpers > rust: helpers: Add i8/i16 atomic xchg_release helpers > rust: helpers: Add i8/i16 atomic xchg_relaxed helpers > > rust/helpers/atomic_ext.c | 41 +++++++++++++++++++++++++++++++++++++++ > 1 file changed, 41 insertions(+) > > > base-commit: 02c5c8c11bbd34cdd9c566dd4ecca48995c09621 > -- > 2.43.0 >