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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?JAWgV53TD5dDo9+FtNTZsv+Ik3Wzu2UNBDQiMTHIaNYrQWrU9sp06BRhq9U5?= =?us-ascii?Q?XD5HkZpymeZ1rNzqTK+8JEC63MrFMXqWRYMIa1/22EhpAew6tiPB5oCstp6N?= =?us-ascii?Q?OnKeMtGjyBXv2uVItNS0Uo5etHN6352PvlZ/7iqNifvfd9hNlFds8RMOvCHj?= =?us-ascii?Q?5q6kTvLqe8gdwXWlCbDLm5nOA1w+wQflXb/X1lJgHbqrGywphX0j5DnrI4ST?= =?us-ascii?Q?TaQjQu6t01B1b3HHyuqkNBzktQ5bja06usRQ+te5NS+u/11HBSmSpQi+Cm4a?= =?us-ascii?Q?UkzZpTaqAnqE8m3mYXYTIZ7Uy/hlGcTfjxgknf757r6RsoMicnXwNyOtQXbp?= =?us-ascii?Q?fmEYRaiAiZwXS5dxjt4dzZFGpriv7wOC0xwEBkMlu5nQ30VOWm3t1bslEfLP?= =?us-ascii?Q?qIvJn7mlPqQ4WhbjkbpxR2KIdQO+f9M5ZCq2ElCGpi/nhYykLCJ4cVqBcN5E?= =?us-ascii?Q?53Ru79oB9NJFJxAM9MoNIwD+mOOr3MH6Q6TLlCPC89v3NDlDF+XRENnX+GJ7?= =?us-ascii?Q?RuP5+GCR6swtX9kYPpmQY0pa+hEABPAZjZUnvn03/AznTfJOgdmy9Fvvijk8?= =?us-ascii?Q?EEB9mMjJtDrwELHdq00U65mJbwBcqCm+C6/1DYbcNzG/8CgLDOdjc/gG3Yl0?= =?us-ascii?Q?lrfUJvM0rPO/op1A93ABFpH9mTboQPzx0HopH4gx3vrZwmVJ2VLb8BTFsFsM?= =?us-ascii?Q?koYZhAOz02YlHJlynY0u+Cne8TyLK/kJPUAaEIr7uusIQ7HpR0r5QBkkBe97?= =?us-ascii?Q?dnCKfWTujO4Vn80Vy25q+x43ZXw0LY4e4nI+LsZGM5fqcaRVJqO9Po7S/fAt?= =?us-ascii?Q?c0QJGdG++F28XjbeHpZGnEiouQX6EmvvCdAyxpNM11IQ95y6zbURQxn9aavn?= =?us-ascii?Q?lQLvPZL3NYGQxeyb7B2U2NEeajiLiuMKuIIc+jKmWGp8zqCed4oTBiNbAF3N?= =?us-ascii?Q?4O1OmQyxICoKR1TGyvFUUxrkARLwdOG59WTqKUKsA4jnneddiZtQO8LtZ6kq?= =?us-ascii?Q?V/3W4fsi0eAKVv+BmsOJ8kggQuPc7s5e7ouQI0E/Nemr6u5dUaPH24757r/l?= =?us-ascii?Q?SDt61tWpLeagGdRGpJnHWEtLQj5wvnjCzwroYeNC/PvV/vqnurjM27zdWxxK?= =?us-ascii?Q?r8Eiqi0+w6aFCrLdgrjNwj2Pqv95uZKKG9lC/MbwE3/UVupHRL91fPelDc2o?= =?us-ascii?Q?jJW8YI+/ycJICmyDjW027TfPGvQJmD5kNGb0F3frVTF0tiowIjjPk30J3vqE?= =?us-ascii?Q?tA9GJtffyaQGv1z+sHJmsQeG4yeBsMcqL95EBDNLh4a6WWTe/M3voZqRLsZZ?= =?us-ascii?Q?izOIjENOkUY7pZlyse/5cQUhb+pwLe2E1m9nfEQq7hjFu7hK8KigTOe2/ekr?= =?us-ascii?Q?ahRzQszdBTaPDe6dx9SBYS0PriLR7kA2SOS6mVPtYvWmj1MuidsBXNhLsuNq?= =?us-ascii?Q?0ltD+6yoPWK/gVXUB+U6GLGptn1XhhQ/jOMcwbGyQ01vafLQijm+SsSDnIDA?= =?us-ascii?Q?qrNDdxO/KwM8bZBddUmUI2WIT6J80gEJlPYZ8IIHSQ9aphS5Ouc+DV5H9g76?= =?us-ascii?Q?5Hri1FTP0b/I14YEWLNL36pL9GxdPJ8vj6xytKvV?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: dcccb4d1-ec10-41b8-60ab-08dd76c200de X-MS-Exchange-CrossTenant-AuthSource: CH3PR12MB8659.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Apr 2025 17:22:57.0178 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 7n06pLixd1e8bc4Jfi23VQHUFLpzoFk5ifE7uQE/WCCIt7bIkQ7gcVVjfnGfHLyI X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6330 The core atomic code has a number of macros where it elaborates architecture primitives into more functions. ARC uses arch_atomic64_cmpxchg() as it's architecture primitive which disable alot of the additional functions. Instead provide arch_cmpxchg64_relaxed() as the primitive and rely on the core macros to create arch_cmpxchg64(). The macros will also provide other functions, for instance, try_cmpxchg64_release(), giving a more complete implementation. Suggested-by: Mark Rutland Link: https://lore.kernel.org/r/Z0747n5bSep4_1VX@J2N7QTR9R3 Signed-off-by: Jason Gunthorpe --- arch/arc/include/asm/atomic64-arcv2.h | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/arch/arc/include/asm/atomic64-arcv2.h b/arch/arc/include/asm/atomic64-arcv2.h index 9b5791b8547133..73080a664369b4 100644 --- a/arch/arc/include/asm/atomic64-arcv2.h +++ b/arch/arc/include/asm/atomic64-arcv2.h @@ -137,12 +137,9 @@ ATOMIC64_OPS(xor, xor, xor) #undef ATOMIC64_OP_RETURN #undef ATOMIC64_OP -static inline s64 -arch_atomic64_cmpxchg(atomic64_t *ptr, s64 expected, s64 new) +static inline u64 __arch_cmpxchg64_relaxed(volatile void *ptr, u64 old, u64 new) { - s64 prev; - - smp_mb(); + u64 prev; __asm__ __volatile__( "1: llockd %0, [%1] \n" @@ -152,14 +149,12 @@ arch_atomic64_cmpxchg(atomic64_t *ptr, s64 expected, s64 new) " bnz 1b \n" "2: \n" : "=&r"(prev) - : "r"(ptr), "ir"(expected), "r"(new) - : "cc"); /* memory clobber comes from smp_mb() */ - - smp_mb(); + : "r"(ptr), "ir"(old), "r"(new) + : "memory", "cc"); return prev; } -#define arch_atomic64_cmpxchg arch_atomic64_cmpxchg +#define arch_cmpxchg64_relaxed __arch_cmpxchg64_relaxed static inline s64 arch_atomic64_xchg(atomic64_t *ptr, s64 new) { base-commit: ea8f6ee2111cd78b32d0363ea630ba9b08ada22d -- 2.43.0