patches.lists.linux.dev archive mirror
 help / color / mirror / Atom feed
From: Jason Gunthorpe <jgg@nvidia.com>
To: Lu Baolu <baolu.lu@linux.intel.com>,
	David Woodhouse <dwmw2@infradead.org>,
	iommu@lists.linux.dev, Joerg Roedel <joro@8bytes.org>,
	Robin Murphy <robin.murphy@arm.com>,
	Will Deacon <will@kernel.org>
Cc: Kevin Tian <kevin.tian@intel.com>,
	patches@lists.linux.dev, Tina Zhang <tina.zhang@intel.com>,
	Wei Wang <wei.w.wang@intel.com>
Subject: [PATCH v2 00/10] Convert Intel VT-D to use the generic iommu page table
Date: Tue, 26 Aug 2025 14:26:23 -0300	[thread overview]
Message-ID: <0-v2-44d4d9e727e7+18ad8-iommu_pt_vtd_jgg@nvidia.com> (raw)

Replace the VT-D iommu_domain implementation of the VTD second stage and
first stage page tables with the iommupt VTDSS and x86_64
pagetables. x86_64 is shared with the AMD driver.

VT-D has HW that requires an incoherent page table walker, the majority of
the patches are adding generic support for the required cache flushing to
iommupt. This is modeled after the existing ARM64 version and is intended
to be re-used there.

Applies on top of the AMD conversion:
  https://patch.msgid.link/r/0-v2-5c26bde5c22d+58b-iommu_pt_jgg@nvidia.com

This is on github: https://github.com/jgunthorpe/linux/commits/iommu_pt_vtd

v2:
 - s/!IS_ENABLED(CONFIG_X86)/IOMMU_PAGES_USE_DMA_API/
 - Update comments
 - Update ignored bits for VTDSS
 - Fix PT_FEAT_VTDSS_FORCE_WRITEABLE
 - New patch to reflow how PT_FEAT_DMA_INCOHERENT reaches the PASID entry
v1: https://patch.msgid.link/r/0-v1-bdb01ffac49c+be-iommu_pt_vtd_jgg@nvidia.com

Jason Gunthorpe (10):
  iommu/pages: Add support for a incoherent IOMMU page walker
  iommupt: Add basic support for SW bits in the page table
  iommupt: Use the incoherent start/stop functions for
    PT_FEAT_DMA_INCOHERENT
  iommupt: Flush the CPU cache after any writes to the page table
  iommupt: Add the Intel VT-D second stage page table format
  iommupt/x86: Set the dirty bit only for writable PTEs
  iommupt/x86: Support SW bits and permit PT_FEAT_DMA_INCOHERENT
  iommu/vt-d: Use the generic iommu page table
  iommu/vt-d: Follow PT_FEAT_DMA_INCOHERENT into the PASID entry
  iommupt: Add a kunit test for the SW bits

 drivers/iommu/generic_pt/.kunitconfig       |   1 +
 drivers/iommu/generic_pt/Kconfig            |  11 +
 drivers/iommu/generic_pt/fmt/Makefile       |   2 +
 drivers/iommu/generic_pt/fmt/defs_vtdss.h   |  21 +
 drivers/iommu/generic_pt/fmt/iommu_vtdss.c  |  10 +
 drivers/iommu/generic_pt/fmt/iommu_x86_64.c |   2 +-
 drivers/iommu/generic_pt/fmt/vtdss.h        | 289 +++++++
 drivers/iommu/generic_pt/fmt/x86_64.h       |  31 +-
 drivers/iommu/generic_pt/iommu_pt.h         | 137 ++-
 drivers/iommu/generic_pt/kunit_generic_pt.h | 110 +++
 drivers/iommu/generic_pt/kunit_iommu.h      |   1 +
 drivers/iommu/generic_pt/pt_common.h        |  29 +
 drivers/iommu/generic_pt/pt_defs.h          |   3 +
 drivers/iommu/generic_pt/pt_fmt_defaults.h  |  62 ++
 drivers/iommu/intel/Kconfig                 |   4 +
 drivers/iommu/intel/iommu.c                 | 900 ++++----------------
 drivers/iommu/intel/iommu.h                 |  99 +--
 drivers/iommu/intel/nested.c                |   5 -
 drivers/iommu/intel/pasid.c                 |  44 +-
 drivers/iommu/intel/pasid.h                 |   1 +
 drivers/iommu/intel/svm.c                   |   1 +
 drivers/iommu/iommu-pages.c                 | 117 +++
 drivers/iommu/iommu-pages.h                 |  45 +-
 include/linux/generic_pt/common.h           |  24 +
 include/linux/generic_pt/iommu.h            |  18 +
 25 files changed, 1077 insertions(+), 890 deletions(-)
 create mode 100644 drivers/iommu/generic_pt/fmt/defs_vtdss.h
 create mode 100644 drivers/iommu/generic_pt/fmt/iommu_vtdss.c
 create mode 100644 drivers/iommu/generic_pt/fmt/vtdss.h


base-commit: 2265e2af0b8fb7314f9be9abd1270557824a045c
-- 
2.43.0


             reply	other threads:[~2025-08-26 17:26 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-26 17:26 Jason Gunthorpe [this message]
2025-08-26 17:26 ` [PATCH v2 01/10] iommu/pages: Add support for a incoherent IOMMU page walker Jason Gunthorpe
2025-08-26 17:26 ` [PATCH v2 02/10] iommupt: Add basic support for SW bits in the page table Jason Gunthorpe
2025-08-26 17:26 ` [PATCH v2 03/10] iommupt: Use the incoherent start/stop functions for PT_FEAT_DMA_INCOHERENT Jason Gunthorpe
2025-08-26 17:26 ` [PATCH v2 04/10] iommupt: Flush the CPU cache after any writes to the page table Jason Gunthorpe
2025-08-26 17:26 ` [PATCH v2 05/10] iommupt: Add the Intel VT-D second stage page table format Jason Gunthorpe
2025-08-26 17:26 ` [PATCH v2 06/10] iommupt/x86: Set the dirty bit only for writable PTEs Jason Gunthorpe
2025-08-26 17:26 ` [PATCH v2 07/10] iommupt/x86: Support SW bits and permit PT_FEAT_DMA_INCOHERENT Jason Gunthorpe
2025-08-26 17:26 ` [PATCH v2 08/10] iommu/vt-d: Use the generic iommu page table Jason Gunthorpe
2025-08-26 17:26 ` [PATCH v2 09/10] iommu/vt-d: Follow PT_FEAT_DMA_INCOHERENT into the PASID entry Jason Gunthorpe
2025-08-26 17:26 ` [PATCH v2 10/10] iommupt: Add a kunit test for the SW bits Jason Gunthorpe

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=0-v2-44d4d9e727e7+18ad8-iommu_pt_vtd_jgg@nvidia.com \
    --to=jgg@nvidia.com \
    --cc=baolu.lu@linux.intel.com \
    --cc=dwmw2@infradead.org \
    --cc=iommu@lists.linux.dev \
    --cc=joro@8bytes.org \
    --cc=kevin.tian@intel.com \
    --cc=patches@lists.linux.dev \
    --cc=robin.murphy@arm.com \
    --cc=tina.zhang@intel.com \
    --cc=wei.w.wang@intel.com \
    --cc=will@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).