From: Baolu Lu <baolu.lu@linux.intel.com>
To: Jason Gunthorpe <jgg@nvidia.com>
Cc: David Woodhouse <dwmw2@infradead.org>,
iommu@lists.linux.dev, Joerg Roedel <joro@8bytes.org>,
Robin Murphy <robin.murphy@arm.com>,
Will Deacon <will@kernel.org>, Kevin Tian <kevin.tian@intel.com>,
patches@lists.linux.dev, Tina Zhang <tina.zhang@intel.com>,
Wei Wang <wei.w.wang@intel.com>
Subject: Re: [PATCH v2 04/10] iommupt: Flush the CPU cache after any writes to the page table
Date: Wed, 24 Sep 2025 11:05:36 +0800 [thread overview]
Message-ID: <13fe8484-c010-44ad-ba9a-a742da791f03@linux.intel.com> (raw)
In-Reply-To: <20250923141340.GO1391379@nvidia.com>
On 9/23/25 22:13, Jason Gunthorpe wrote:
> On Tue, Sep 23, 2025 at 10:29:21AM +0800, Baolu Lu wrote:
>> On 9/22/25 22:44, Jason Gunthorpe wrote:
>>> On Mon, Sep 22, 2025 at 10:31:49AM +0800, Baolu Lu wrote:
>>>> On 8/27/25 01:26, Jason Gunthorpe wrote:
>>>>> @@ -585,6 +635,7 @@ static __always_inline int __do_map_single_page(struct pt_range *range,
>>>>> return -EADDRINUSE;
>>>>> pt_install_leaf_entry(&pts, map->oa, PAGE_SHIFT,
>>>>> &map->attrs);
>>>>> + /* No flush, not used when incoherent */
>>>>> map->oa += PAGE_SIZE;
>>>>> return 0;
>>>>> }
>>>>> @@ -811,7 +862,8 @@ int DOMAIN_NS(map_pages)(struct iommu_domain *domain, unsigned long iova,
>>>>> PT_WARN_ON(map.leaf_level > range.top_level);
>>>>> do {
>>>>> - if (single_page) {
>>>>> + if (single_page &&
>>>>> + !pt_feature(common, PT_FEAT_DMA_INCOHERENT)) {
>>>>> ret = pt_walk_range(&range, __map_single_page, &map);
>>>>> if (ret != -EAGAIN)
>>>>> break;
>>>> I don't follow the single_page logic here. Why is single_page exclusive
>>>> with PT_FEAT_DMA_INCOHERENT? To my understanding, PT_FEAT_DMA_INCOHERENT
>>>> has no relationship with how the page table is organized. Could you
>>>> elaborate a bit?
>>> It is this comment above:
>>>
>>> /* No flush, not used when incoherent */
>>>
>>> __do_map_single_page() doesn't implement the coherency logic. As an
>>> agressive inline I didn't want to bloat it.
>> But, is that functionally correct, though?
> It is functionally correct because it is never called on incoherent
> configurations 🙂
>
>> In the incoherent case, even
>> if a leaf page entry is changed, the cache should be flushed so that the
>> hardware can see the change.
> Yes, and since the code doesn't do this it isn't called in that case
> otherwise it is a functional problem.
>
>> Basically, I don't understand why
>> __do_map_single_page() is "not used when incoherent". I must have
>> overlooked something. 🙂
> Basically it is an optimization and we disable the optimization on
> incoherent. It is disabled because implementing the flushing would
> bloat the code undesirably.
Oh, I see! __do_map_single_page() is actually a fast path. We disabled
this fast path for the incoherent case due to the cache flushing
behavior. Thanks for the explanation.
Thanks,
baolu
next prev parent reply other threads:[~2025-09-24 3:08 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-26 17:26 [PATCH v2 00/10] Convert Intel VT-D to use the generic iommu page table Jason Gunthorpe
2025-08-26 17:26 ` [PATCH v2 01/10] iommu/pages: Add support for a incoherent IOMMU page walker Jason Gunthorpe
2025-09-21 9:54 ` Baolu Lu
2025-09-22 16:32 ` Jason Gunthorpe
2025-10-14 7:41 ` Tian, Kevin
2025-08-26 17:26 ` [PATCH v2 02/10] iommupt: Add basic support for SW bits in the page table Jason Gunthorpe
2025-09-21 10:21 ` Baolu Lu
2025-10-14 7:45 ` Tian, Kevin
2025-10-21 13:18 ` Jason Gunthorpe
2025-08-26 17:26 ` [PATCH v2 03/10] iommupt: Use the incoherent start/stop functions for PT_FEAT_DMA_INCOHERENT Jason Gunthorpe
2025-09-21 13:29 ` Baolu Lu
2025-10-14 7:51 ` Tian, Kevin
2025-10-21 13:20 ` Jason Gunthorpe
2025-08-26 17:26 ` [PATCH v2 04/10] iommupt: Flush the CPU cache after any writes to the page table Jason Gunthorpe
2025-09-22 2:12 ` Baolu Lu
2025-09-22 14:42 ` Jason Gunthorpe
2025-09-23 2:17 ` Baolu Lu
2025-09-23 14:10 ` Jason Gunthorpe
2025-09-24 2:30 ` Baolu Lu
2025-09-22 2:31 ` Baolu Lu
2025-09-22 14:44 ` Jason Gunthorpe
2025-09-23 2:29 ` Baolu Lu
2025-09-23 14:13 ` Jason Gunthorpe
2025-09-24 3:05 ` Baolu Lu [this message]
2025-10-14 7:53 ` Tian, Kevin
2025-10-21 13:50 ` Jason Gunthorpe
2025-08-26 17:26 ` [PATCH v2 05/10] iommupt: Add the Intel VT-D second stage page table format Jason Gunthorpe
2025-09-22 3:06 ` Baolu Lu
2025-10-14 7:54 ` Tian, Kevin
2025-10-21 13:58 ` Jason Gunthorpe
2025-08-26 17:26 ` [PATCH v2 06/10] iommupt/x86: Set the dirty bit only for writable PTEs Jason Gunthorpe
2025-10-14 7:55 ` Tian, Kevin
2025-08-26 17:26 ` [PATCH v2 07/10] iommupt/x86: Support SW bits and permit PT_FEAT_DMA_INCOHERENT Jason Gunthorpe
2025-10-14 7:55 ` Tian, Kevin
2025-08-26 17:26 ` [PATCH v2 08/10] iommu/vt-d: Use the generic iommu page table Jason Gunthorpe
2025-09-22 11:17 ` Baolu Lu
2025-10-14 7:55 ` Tian, Kevin
2025-08-26 17:26 ` [PATCH v2 09/10] iommu/vt-d: Follow PT_FEAT_DMA_INCOHERENT into the PASID entry Jason Gunthorpe
2025-09-22 13:00 ` Baolu Lu
2025-10-14 7:58 ` Tian, Kevin
2025-08-26 17:26 ` [PATCH v2 10/10] iommupt: Add a kunit test for the SW bits Jason Gunthorpe
2025-10-14 7:58 ` Tian, Kevin
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