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From: Baolu Lu <baolu.lu@linux.intel.com>
To: Jason Gunthorpe <jgg@nvidia.com>,
	David Woodhouse <dwmw2@infradead.org>,
	iommu@lists.linux.dev, Joerg Roedel <joro@8bytes.org>,
	Robin Murphy <robin.murphy@arm.com>,
	Will Deacon <will@kernel.org>
Cc: Kevin Tian <kevin.tian@intel.com>,
	patches@lists.linux.dev, Tina Zhang <tina.zhang@intel.com>,
	Wei Wang <wei.w.wang@intel.com>
Subject: Re: [PATCH 7/9] iommupt/x86: Support SW bits and permit PT_FEAT_DMA_INCOHERENT
Date: Tue, 22 Jul 2025 13:17:59 +0800	[thread overview]
Message-ID: <158774a0-824f-42a7-93c9-fb1e0d258cc7@linux.intel.com> (raw)
In-Reply-To: <7-v1-bdb01ffac49c+be-iommu_pt_vtd_jgg@nvidia.com>

On 7/17/25 03:57, Jason Gunthorpe wrote:
> VT-D requires PT_FEAT_DMA_INCOHERENT for the x86 page table as well,
> implement the required SW bits and enable the feature.
> 
> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
> ---
>   drivers/iommu/generic_pt/fmt/iommu_x86_64.c |  2 +-
>   drivers/iommu/generic_pt/fmt/x86_64.h       | 27 +++++++++++++++++++++
>   2 files changed, 28 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/iommu/generic_pt/fmt/iommu_x86_64.c b/drivers/iommu/generic_pt/fmt/iommu_x86_64.c
> index 5c5960d871a32f..5472660c2d7156 100644
> --- a/drivers/iommu/generic_pt/fmt/iommu_x86_64.c
> +++ b/drivers/iommu/generic_pt/fmt/iommu_x86_64.c
> @@ -6,6 +6,6 @@
>   #define PT_SUPPORTED_FEATURES                                  \
>   	(BIT(PT_FEAT_SIGN_EXTEND) | BIT(PT_FEAT_FLUSH_RANGE) | \
>   	 BIT(PT_FEAT_FLUSH_RANGE_NO_GAPS) |                    \
> -	 BIT(PT_FEAT_X86_64_AMD_ENCRYPT_TABLES))
> +	 BIT(PT_FEAT_X86_64_AMD_ENCRYPT_TABLES) | BIT(PT_FEAT_DMA_INCOHERENT))
>   
>   #include "iommu_template.h"
> diff --git a/drivers/iommu/generic_pt/fmt/x86_64.h b/drivers/iommu/generic_pt/fmt/x86_64.h
> index 60f8bd6b164b54..1b691f7cbf82d8 100644
> --- a/drivers/iommu/generic_pt/fmt/x86_64.h
> +++ b/drivers/iommu/generic_pt/fmt/x86_64.h
> @@ -160,6 +160,33 @@ static inline void x86_64_pt_attr_from_entry(const struct pt_state *pts,
>   }
>   #define pt_attr_from_entry x86_64_pt_attr_from_entry
>   
> +static inline unsigned int x86_64_pt_max_sw_bit(struct pt_common *common)
> +{
> +	return 12;
> +}
> +#define pt_max_sw_bit x86_64_pt_max_sw_bit
> +
> +static inline u64 x86_64_pt_sw_bit(unsigned int bitnr)
> +{
> +	/* Bits marked Ignored/AVL in the specification */
> +	switch (bitnr) {
> +	case 0:
> +		return BIT(9);
> +	case 1:
> +		return BIT(11);
> +	case 2 ... 12:
> +		return BIT_ULL((bitnr - 2) + 52);

Just out of curiosity, why bit 63 can't be used as the sw bit?

> +	/* Remaing bits 9-8,6,4,3  are only available in some entries */
> +	default:
> +		if (__builtin_constant_p(bitnr))
> +			BUILD_BUG();
> +		else
> +			PT_WARN_ON(true);
> +		return 0;
> +	}
> +}
> +#define pt_sw_bit x86_64_pt_sw_bit
> +
>   /* --- iommu */
>   #include <linux/generic_pt/iommu.h>
>   #include <linux/iommu.h>

Looks good to me.

Reviewed-by: Lu Baolu <baolu.lu@linux.intel.com>

Thanks,
baolu

  reply	other threads:[~2025-07-22  5:20 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-07-16 19:57 [PATCH 0/9] Convert Intel VT-D to use the generic iommu page table Jason Gunthorpe
2025-07-16 19:57 ` [PATCH 1/9] iommu/pages: Add support for a incoherent IOMMU page walker Jason Gunthorpe
2025-07-21  8:41   ` Baolu Lu
2025-07-29 22:32     ` Jason Gunthorpe
2025-07-30  1:49       ` Baolu Lu
2025-08-11 21:21         ` Jason Gunthorpe
2025-08-15 11:28   ` Tian, Kevin
2025-08-22 21:13     ` Jason Gunthorpe
2025-07-16 19:57 ` [PATCH 2/9] iommupt: Add basic support for SW bits in the page table Jason Gunthorpe
2025-08-15 11:29   ` Tian, Kevin
2025-08-18 23:35     ` Jason Gunthorpe
2025-07-16 19:57 ` [PATCH 3/9] iommupt: Use the incoherent start/stop functions for PT_FEAT_DMA_INCOHERENT Jason Gunthorpe
2025-08-15 11:35   ` Tian, Kevin
2025-08-22 20:45     ` Jason Gunthorpe
2025-07-16 19:57 ` [PATCH 4/9] iommupt: Flush the CPU cache after any writes to the page table Jason Gunthorpe
2025-07-16 19:57 ` [PATCH 5/9] iommupt: Add the Intel VT-D second stage page table format Jason Gunthorpe
2025-07-22  3:11   ` Baolu Lu
2025-07-29 23:05     ` Jason Gunthorpe
2025-07-30  2:00       ` Baolu Lu
2025-08-22  9:14   ` Tian, Kevin
2025-08-22 14:53     ` Jason Gunthorpe
2025-07-16 19:57 ` [PATCH 6/9] iommupt/x86: Set the dirty bit only for writable PTEs Jason Gunthorpe
2025-07-21 10:02   ` Baolu Lu
2025-07-16 19:57 ` [PATCH 7/9] iommupt/x86: Support SW bits and permit PT_FEAT_DMA_INCOHERENT Jason Gunthorpe
2025-07-22  5:17   ` Baolu Lu [this message]
2025-07-29 23:13     ` Jason Gunthorpe
2025-07-30  2:35       ` Baolu Lu
2025-08-22  9:17   ` Tian, Kevin
2025-08-22 14:55     ` Jason Gunthorpe
2025-07-16 19:57 ` [PATCH 8/9] iommu/vt-d: Use the generic iommu page table Jason Gunthorpe
2025-07-22  6:44   ` Baolu Lu
2025-07-29 23:39     ` Jason Gunthorpe
2025-08-22  9:35   ` Tian, Kevin
2025-08-22 20:43     ` Jason Gunthorpe
2025-07-16 19:57 ` [PATCH 9/9] iommupt: Add a kunit test for the SW bits Jason Gunthorpe

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