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From: Reinette Chatre <reinette.chatre@intel.com>
To: "Chen, Zide" <zide.chen@intel.com>, <shuah@kernel.org>,
	<Dave.Martin@arm.com>, <james.morse@arm.com>,
	<tony.luck@intel.com>, <peternewman@google.com>,
	<babu.moger@amd.com>, <ilpo.jarvinen@linux.intel.com>
Cc: <dapeng1.mi@linux.intel.com>, <fenghuay@nvidia.com>,
	<linux-kselftest@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<patches@lists.linux.dev>
Subject: Re: [PATCH 3/8] selftests/resctrl: Support multiple events associated with iMC
Date: Wed, 11 Feb 2026 19:54:12 -0800	[thread overview]
Message-ID: <1c3574bf-93b9-4f01-bd69-bea5e69da8ae@intel.com> (raw)
In-Reply-To: <ee039e1a-d2aa-4387-ab62-00d425e46423@intel.com>

Hi Zide,

On 2/11/26 3:37 PM, Chen, Zide wrote:
> 
> 
> On 2/10/2026 8:50 AM, Reinette Chatre wrote:
>> The resctrl selftests discover needed parameters to perf_event_open() via
>> sysfs. The PMU associated with every memory controller (iMC) is discovered
>> via the /sys/bus/event_source/devices/uncore_imc_N/type file while
>> the read memory bandwidth event type and umask is discovered via
>> /sys/bus/event_source/devices/uncore_imc_N/events/cas_count_read.
>>
>> Newer systems may have multiple events that expose read memory bandwidth.
>> For example,
>>  /sys/bus/event_source/devices/uncore_imc_N/events/cas_count_read_sch0
>>  /sys/bus/event_source/devices/uncore_imc_N/events/cas_count_read_sch1
>>
>> Support parsing of iMC PMU properties when the PMU may have multiple events
>> to measure read memory bandwidth. The PMU only needs to be discovered once.
>> Split the parsing of event details from actual PMU discovery in order to
>> loop over all events associated with the PMU. Match all events with the
>> cas_count_read prefix instead of requiring there to be one file with that
>> name.
>>
>> Make the parsing code more robust. With strings passed around to create
>> needed paths, use snprintf() instead of sprintf() to ensure there is
>> always enough space to create the path. Ensure there is enough room in
>> imc_counters_config[] before attempting to add an entry.
>>
>> Signed-off-by: Reinette Chatre <reinette.chatre@intel.com>
> 
> Reviewed-by: Zide Chen <zide.chen@intel.com>

Thank you very much for taking a look at this work and especially thanks
for creating the perf changes that they depend on to fix these tests.

Reinette

  reply	other threads:[~2026-02-12  3:54 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-02-10 16:50 [PATCH 0/8] selftests/resctrl: Fixes and improvements focused on recent Intel platforms Reinette Chatre
2026-02-10 16:50 ` [PATCH 1/8] selftests/resctrl: Do not store iMC counter value in counter config structure Reinette Chatre
2026-02-10 16:50 ` [PATCH 2/8] selftests/resctrl: Prepare for parsing multiple events per iMC Reinette Chatre
2026-02-11 23:37   ` Chen, Zide
2026-02-12  3:52     ` Reinette Chatre
2026-02-10 16:50 ` [PATCH 3/8] selftests/resctrl: Support multiple events associated with iMC Reinette Chatre
2026-02-11 23:37   ` Chen, Zide
2026-02-12  3:54     ` Reinette Chatre [this message]
2026-02-10 16:50 ` [PATCH 4/8] selftests/resctrl: Increase size of buffer used in MBM and MBA tests Reinette Chatre
2026-02-10 16:50 ` [PATCH 5/8] selftests/resctrl: Raise threshold at which MBM and PMU values are compared Reinette Chatre
2026-02-10 16:50 ` [PATCH 6/8] selftests/resctrl: Remove requirement on cache miss rate Reinette Chatre
2026-02-10 16:50 ` [PATCH 7/8] selftests/resctrl: Simplify perf usage in CAT test Reinette Chatre
2026-02-10 16:50 ` [PATCH 8/8] selftests/resctrl: Reduce L2 impact on " Reinette Chatre

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