From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E313128ED for ; Mon, 12 Dec 2022 13:35:31 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5E75BC43392; Mon, 12 Dec 2022 13:35:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1670852131; bh=yHbMGquTZpBdGaMsjnRtRspLMqIM4gl7RM/XsSw8k/g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=purEw7ZIRNaiWdiy9Q9wEm6M+hiU/0/zb04IorV1isLajUi/xuHcMhbgq1g4Dmmvi 7V5cpACn1y3tV66swMznjR0y0BZfghg+4CfrJYHd96BvotUrcYGEI9qKI7CPaCelsd 27DoygLLDUFd3l6bc4zavtTabwOtp0lU7mTX9wUw= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Chancel Liu , Charles Keepax , Mark Brown , Sasha Levin Subject: [PATCH 6.0 018/157] ASoC: wm8962: Wait for updated value of WM8962_CLOCKING1 register Date: Mon, 12 Dec 2022 14:16:06 +0100 Message-Id: <20221212130935.173174846@linuxfoundation.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221212130934.337225088@linuxfoundation.org> References: <20221212130934.337225088@linuxfoundation.org> User-Agent: quilt/0.67 Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Chancel Liu [ Upstream commit 3ca507bf99611c82dafced73e921c1b10ee12869 ] DSPCLK_DIV field in WM8962_CLOCKING1 register is used to generate correct frequency of LRCLK and BCLK. Sometimes the read-only value can't be updated timely after enabling SYSCLK. This results in wrong calculation values. Delay is introduced here to wait for newest value from register. The time of the delay should be at least 500~1000us according to test. Signed-off-by: Chancel Liu Acked-by: Charles Keepax Link: https://lore.kernel.org/r/20221109121354.123958-1-chancel.liu@nxp.com Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- sound/soc/codecs/wm8962.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/sound/soc/codecs/wm8962.c b/sound/soc/codecs/wm8962.c index 6df06fba4377..ee1cad5af535 100644 --- a/sound/soc/codecs/wm8962.c +++ b/sound/soc/codecs/wm8962.c @@ -2503,6 +2503,14 @@ static void wm8962_configure_bclk(struct snd_soc_component *component) snd_soc_component_update_bits(component, WM8962_CLOCKING2, WM8962_SYSCLK_ENA_MASK, WM8962_SYSCLK_ENA); + /* DSPCLK_DIV field in WM8962_CLOCKING1 register is used to generate + * correct frequency of LRCLK and BCLK. Sometimes the read-only value + * can't be updated timely after enabling SYSCLK. This results in wrong + * calculation values. Delay is introduced here to wait for newest + * value from register. The time of the delay should be at least + * 500~1000us according to test. + */ + usleep_range(500, 1000); dspclk = snd_soc_component_read(component, WM8962_CLOCKING1); if (snd_soc_component_get_bias_level(component) != SND_SOC_BIAS_ON) -- 2.35.1