From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 342141875 for ; Wed, 28 Dec 2022 15:52:35 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A68DDC433D2; Wed, 28 Dec 2022 15:52:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1672242755; bh=jwhWFO95Z5txRdFKTTaHRjRyqj17/pJyEnieqZZEd2Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=179IouAIqV6evsSty/6tArKF3mhXWurTmCWOjfkCg6/y1UIFhKQS2H7beLIuPdhOZ ZgYxb+iQqStrXevHOyCaHGH55e17/TUlrDxf+pYuKWsQ+XMwTfTbYZ6Z5RzbI40KBk 5NpGsyND7LVSMK/IwNH7pF3pQD5gMfem5nLfUC8s= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Rob Herring , Taniya Das , Stephen Boyd , Bjorn Andersson , Sasha Levin Subject: [PATCH 6.0 0448/1073] dt-bindings: clock: Add resets for LPASS audio clock controller for SC7280 Date: Wed, 28 Dec 2022 15:33:56 +0100 Message-Id: <20221228144340.200778866@linuxfoundation.org> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221228144328.162723588@linuxfoundation.org> References: <20221228144328.162723588@linuxfoundation.org> User-Agent: quilt/0.67 Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Taniya Das [ Upstream commit be9439df235352a41605bf2cc8ba10aa0fc40d29 ] Add support for LPASS audio clock gating for RX/TX/SWA core bus clocks for SC7280. Update reg property min/max items in YAML schema. Fixes: 4185b27b3bef ("dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280") Acked-by: Rob Herring Signed-off-by: Taniya Das Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1662005846-4838-4-git-send-email-quic_c_skakit@quicinc.com Stable-dep-of: d470be3c4f30 ("clk: qcom: lpass-sc7280: Fix pm_runtime usage") Signed-off-by: Sasha Levin --- .../clock/qcom,sc7280-lpasscorecc.yaml | 19 ++++++++++++++++--- .../clock/qcom,lpassaudiocc-sc7280.h | 5 +++++ 2 files changed, 21 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml index bad9135489de..1d20cdcc69ff 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml @@ -22,6 +22,8 @@ properties: clock-names: true + reg: true + compatible: enum: - qcom,sc7280-lpassaoncc @@ -38,8 +40,8 @@ properties: '#power-domain-cells': const: 1 - reg: - maxItems: 1 + '#reset-cells': + const: 1 required: - compatible @@ -69,6 +71,11 @@ allOf: items: - const: bi_tcxo - const: lpass_aon_cc_main_rcg_clk_src + + reg: + items: + - description: lpass core cc register + - description: lpass audio csr register - if: properties: compatible: @@ -90,6 +97,8 @@ allOf: - const: bi_tcxo_ao - const: iface + reg: + maxItems: 1 - if: properties: compatible: @@ -108,6 +117,8 @@ allOf: items: - const: bi_tcxo + reg: + maxItems: 1 examples: - | #include @@ -116,13 +127,15 @@ examples: #include lpass_audiocc: clock-controller@3300000 { compatible = "qcom,sc7280-lpassaudiocc"; - reg = <0x3300000 0x30000>; + reg = <0x3300000 0x30000>, + <0x32a9000 0x1000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; #clock-cells = <1>; #power-domain-cells = <1>; + #reset-cells = <1>; }; - | diff --git a/include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h b/include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h index 20ef2ea673f3..22dcd47d4513 100644 --- a/include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h +++ b/include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h @@ -24,6 +24,11 @@ #define LPASS_AUDIO_CC_RX_MCLK_CLK 14 #define LPASS_AUDIO_CC_RX_MCLK_CLK_SRC 15 +/* LPASS AUDIO CC CSR */ +#define LPASS_AUDIO_SWR_RX_CGCR 0 +#define LPASS_AUDIO_SWR_TX_CGCR 1 +#define LPASS_AUDIO_SWR_WSA_CGCR 2 + /* LPASS_AON_CC clocks */ #define LPASS_AON_CC_PLL 0 #define LPASS_AON_CC_PLL_OUT_EVEN 1 -- 2.35.1