From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12AB2CBA1 for ; Tue, 14 Feb 2023 23:45:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1676418356; x=1707954356; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RJlwSFVpT1cewwIwRvUfBxfg5OygWbxR/zFOIt+ZgzQ=; b=fBmXvXqMrciknjoaoYSUUIwgOwWUgjspft3mzWeTE+4G4lyHYE4BXE/R BDowGpBGtLdCRwe+TKHNCCkxClL3z1dbFN72uhVN9dsSfmdWMI1FEXGKH SEqFtbeOmwcGTyldyrKFsO3HDjIgryR2C1bWaTVwo+GWKqH7a4KnuV9qw Y7kDVbGGJt0dyN0ohOZcpGjnEJHfGQv75+Dx23P96Mju16vTnZTg4/nl/ s4AfYoIrR0U4/r7qseYuzFGwI5tFkJAkxPk7BUhYMSf8gfI6wPWubMcrY PONJ4MOMU1Tuo7i9nOMIQMxNe/20Xl1nuIbkmDhKSnFw07Rr1aIUXf/9M Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10621"; a="417522990" X-IronPort-AV: E=Sophos;i="5.97,298,1669104000"; d="scan'208";a="417522990" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Feb 2023 15:45:54 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10621"; a="669391008" X-IronPort-AV: E=Sophos;i="5.97,298,1669104000"; d="scan'208";a="669391008" Received: from jithujos.sc.intel.com ([172.25.103.66]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Feb 2023 15:45:53 -0800 From: Jithu Joseph To: hdegoede@redhat.com, markgross@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, gregkh@linuxfoundation.org, rostedt@goodmis.org, jithu.joseph@intel.com, ashok.raj@intel.com, tony.luck@intel.com, linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, patches@lists.linux.dev, ravi.v.shankar@intel.com, thiago.macieira@intel.com, athenas.jimenez.gonzalez@intel.com, sohil.mehta@intel.com Subject: [PATCH v2 1/7] x86/include/asm/msr-index.h: Add IFS Array test bits Date: Tue, 14 Feb 2023 15:44:20 -0800 Message-Id: <20230214234426.344960-2-jithu.joseph@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230214234426.344960-1-jithu.joseph@intel.com> References: <20230131234302.3997223-1-jithu.joseph@intel.com> <20230214234426.344960-1-jithu.joseph@intel.com> Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Define MSR bitfields for enumerating support for Array BIST test. Signed-off-by: Jithu Joseph Reviewed-by: Tony Luck --- arch/x86/include/asm/msr-index.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index d3fe82c5d6b6..ad8997773ad3 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -197,6 +197,8 @@ /* Abbreviated from Intel SDM name IA32_INTEGRITY_CAPABILITIES */ #define MSR_INTEGRITY_CAPS 0x000002d9 +#define MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT 2 +#define MSR_INTEGRITY_CAPS_ARRAY_BIST BIT(MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT) #define MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT 4 #define MSR_INTEGRITY_CAPS_PERIODIC_BIST BIT(MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT) -- 2.25.1