From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A84C11C29 for ; Mon, 20 Mar 2023 15:14:33 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 28176C4339B; Mon, 20 Mar 2023 15:14:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1679325273; bh=DxuNAsAhsPi84EKZwwBa3O3NPyV17ENS3kdwmD4AvF0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SKL4UrZCMFWVaj6scWJMIAWCkd76WQ3i3oL0jfUOMy9yIEhCKiYb2e1Lwr0xgvGnT 8TBUkoZd/Xo497bL6XYIgXrWVq9gSOgQefcH/F03uxLRbLNR6jFuoqpQ0HTu1YMWR9 GYTi23+yLqlLU86ujGbndIbLvtzdodotpbyFfAXY= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Reima ISHII , Paolo Bonzini Subject: [PATCH 5.15 085/115] KVM: nVMX: add missing consistency checks for CR0 and CR4 Date: Mon, 20 Mar 2023 15:54:57 +0100 Message-Id: <20230320145452.988346384@linuxfoundation.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230320145449.336983711@linuxfoundation.org> References: <20230320145449.336983711@linuxfoundation.org> User-Agent: quilt/0.67 Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Paolo Bonzini commit 112e66017bff7f2837030f34c2bc19501e9212d5 upstream. The effective values of the guest CR0 and CR4 registers may differ from those included in the VMCS12. In particular, disabling EPT forces CR4.PAE=1 and disabling unrestricted guest mode forces CR0.PG=CR0.PE=1. Therefore, checks on these bits cannot be delegated to the processor and must be performed by KVM. Reported-by: Reima ISHII Cc: stable@vger.kernel.org Signed-off-by: Paolo Bonzini Signed-off-by: Greg Kroah-Hartman --- arch/x86/kvm/vmx/nested.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) --- a/arch/x86/kvm/vmx/nested.c +++ b/arch/x86/kvm/vmx/nested.c @@ -2991,7 +2991,7 @@ static int nested_vmx_check_guest_state( struct vmcs12 *vmcs12, enum vm_entry_failure_code *entry_failure_code) { - bool ia32e; + bool ia32e = !!(vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE); *entry_failure_code = ENTRY_FAIL_DEFAULT; @@ -3017,6 +3017,13 @@ static int nested_vmx_check_guest_state( vmcs12->guest_ia32_perf_global_ctrl))) return -EINVAL; + if (CC((vmcs12->guest_cr0 & (X86_CR0_PG | X86_CR0_PE)) == X86_CR0_PG)) + return -EINVAL; + + if (CC(ia32e && !(vmcs12->guest_cr4 & X86_CR4_PAE)) || + CC(ia32e && !(vmcs12->guest_cr0 & X86_CR0_PG))) + return -EINVAL; + /* * If the load IA32_EFER VM-entry control is 1, the following checks * are performed on the field for the IA32_EFER MSR: @@ -3028,7 +3035,6 @@ static int nested_vmx_check_guest_state( */ if (to_vmx(vcpu)->nested.nested_run_pending && (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) { - ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0; if (CC(!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer)) || CC(ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA)) || CC(((vmcs12->guest_cr0 & X86_CR0_PG) &&