From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 98B2D522E for ; Sun, 9 Jul 2023 11:29:39 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 105E2C433C8; Sun, 9 Jul 2023 11:29:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1688902179; bh=B7Dv/CsjcgQoGuP+heAmAmLpwUNdSE9CFfIAgpODInI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=OWck9JxujXonQ/2yJnD7qfCP4Yp2wwPNNP3qVx1bm836tGqWjk7mN1ng99/HZHWx7 vtlj/BV85eg32ClOR/G5g2oKbnPqd38EDt/uJ2GGl0WgDPQaCl29hKAO9fizf76tZG lJiN5r3Ja7pHRa8sw+LWdDtTyCDI0bf9z2yuVpMM= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, David Heidelberg , Dmitry Baryshkov , Konrad Dybcio , Rob Clark , Sasha Levin Subject: [PATCH 6.3 284/431] drm/msm/a6xx: dont set IO_PGTABLE_QUIRK_ARM_OUTER_WBWA with coherent SMMU Date: Sun, 9 Jul 2023 13:13:52 +0200 Message-ID: <20230709111457.803780010@linuxfoundation.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230709111451.101012554@linuxfoundation.org> References: <20230709111451.101012554@linuxfoundation.org> User-Agent: quilt/0.67 Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Dmitry Baryshkov [ Upstream commit 38e27a6fbf2206b18417c5985dbcdeca0f2026b8 ] If the Adreno SMMU is dma-coherent, allocation will fail unless we disable IO_PGTABLE_QUIRK_ARM_OUTER_WBWA. Skip setting this quirk for the coherent SMMUs (like we have on sm8350 platform). Fixes: 54af0ceb7595 ("arm64: dts: qcom: sm8350: add GPU, GMU, GPU CC and SMMU nodes") Reported-by: David Heidelberg Signed-off-by: Dmitry Baryshkov Tested-by: David Heidelberg Reviewed-by: Konrad Dybcio Tested-by: Konrad Dybcio # SM8450 HDK Patchwork: https://patchwork.freedesktop.org/patch/531562/ Signed-off-by: Rob Clark Signed-off-by: Sasha Levin --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 2942d2548ce69..f74495dcbd966 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1793,7 +1793,8 @@ a6xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev) * This allows GPU to set the bus attributes required to use system * cache on behalf of the iommu page table walker. */ - if (!IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice)) + if (!IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice) && + !device_iommu_capable(&pdev->dev, IOMMU_CAP_CACHE_COHERENCY)) quirks |= IO_PGTABLE_QUIRK_ARM_OUTER_WBWA; return adreno_iommu_create_address_space(gpu, pdev, quirks); -- 2.39.2