From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 889AA8F70 for ; Sun, 16 Jul 2023 19:54:49 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0B339C433C8; Sun, 16 Jul 2023 19:54:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1689537289; bh=K1siVKNB3d1m+Yh8/Yfv/RBxHJNTSknrNiMiUqxPb4c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZSQA9XH5hF4abN2AWBGIhCuVeXQiKl+0vm1jgeR7zmj3XbnfDB5L8gUmb6OaIFdQf Yeheqr39NcDysedbFEUjTB1+CcTtRD6k9C5M5DmCLJov05+tUpi41jV9ovg8eeySN8 zVK3htYKYSt0/PhmS8X+lwxwT8sft9JyBqlhNVy4= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, yangqiming , Jianmin Lv , Marc Zyngier , Sasha Levin Subject: [PATCH 6.4 042/800] irqchip/loongson-eiointc: Fix irq affinity setting during resume Date: Sun, 16 Jul 2023 21:38:15 +0200 Message-ID: <20230716194950.071060952@linuxfoundation.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230716194949.099592437@linuxfoundation.org> References: <20230716194949.099592437@linuxfoundation.org> User-Agent: quilt/0.67 Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Jianmin Lv [ Upstream commit fb07b8f83441febeb0daf199b5f18c6de9bbab03 ] The hierarchy of PCH PIC, PCH PCI MSI and EIONTC is as following: PCH PIC ------->| |---->EIOINTC PCH PCI MSI --->| so the irq_data list of irq_desc for IRQs on PCH PIC and PCH PCI MSI is like this: irq_desc->irq_data(domain: PCH PIC)->parent_data(domain: EIOINTC) irq_desc->irq_data(domain: PCH PCI MSI)->parent_data(domain: EIOINTC) In eiointc_resume(), the irq_data passed into eiointc_set_irq_affinity() should be matched to EIOINTC domain instead of PCH PIC or PCH PCI MSI domain, so fix it. Fixes: a90335c2dfb4 ("irqchip/loongson-eiointc: Add suspend/resume support") Reported-by: yangqiming Signed-off-by: Jianmin Lv Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20230614115936.5950-6-lvjianmin@loongson.cn Signed-off-by: Sasha Levin --- drivers/irqchip/irq-loongson-eiointc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-loongson-eiointc.c b/drivers/irqchip/irq-loongson-eiointc.c index 71ef19f77a5a0..a7fcde3e3ecc7 100644 --- a/drivers/irqchip/irq-loongson-eiointc.c +++ b/drivers/irqchip/irq-loongson-eiointc.c @@ -314,7 +314,7 @@ static void eiointc_resume(void) desc = irq_resolve_mapping(eiointc_priv[i]->eiointc_domain, j); if (desc && desc->handle_irq && desc->handle_irq != handle_bad_irq) { raw_spin_lock(&desc->lock); - irq_data = &desc->irq_data; + irq_data = irq_domain_get_irq_data(eiointc_priv[i]->eiointc_domain, irq_desc_get_irq(desc)); eiointc_set_irq_affinity(irq_data, irq_data->common->affinity, 0); raw_spin_unlock(&desc->lock); } -- 2.39.2