From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8830914A81 for ; Thu, 24 Aug 2023 17:20:32 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 09142C433C8; Thu, 24 Aug 2023 17:20:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1692897632; bh=X0cVkb4r82Zd3kACm/BanmPDkq3o6quXZKFtT+9yfQM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=A7rRFyUPDJoNBNIC7q6bL2pCAdJuaob8AgUTshc8v94PThMr+/S7TRPciJNkrLWwi DnOt/E0CJtFSQJ57Iw/Ms1rFh8Ak0mV0FUAfBqfVHKXU16uPvG4m2/FdsVhx4ZzIsK hoqQJzy5UNr9KFy06BDdHd7VLous2aUBKUnx2cj0= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Alfred Lee , Andrew Lunn , Jakub Kicinski , Sasha Levin Subject: [PATCH 5.10 091/135] net: dsa: mv88e6xxx: Wait for EEPROM done before HW reset Date: Thu, 24 Aug 2023 19:09:23 +0200 Message-ID: <20230824170621.202822152@linuxfoundation.org> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230824170617.074557800@linuxfoundation.org> References: <20230824170617.074557800@linuxfoundation.org> User-Agent: quilt/0.67 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 5.10-stable review patch. If anyone has any objections, please let me know. ------------------ From: Alfred Lee [ Upstream commit 23d775f12dcd23d052a4927195f15e970e27ab26 ] If the switch is reset during active EEPROM transactions, as in just after an SoC reset after power up, the I2C bus transaction may be cut short leaving the EEPROM internal I2C state machine in the wrong state. When the switch is reset again, the bad state machine state may result in data being read from the wrong memory location causing the switch to enter unexpected mode rendering it inoperational. Fixes: a3dcb3e7e70c ("net: dsa: mv88e6xxx: Wait for EEPROM done after HW reset") Signed-off-by: Alfred Lee Reviewed-by: Andrew Lunn Link: https://lore.kernel.org/r/20230815001323.24739-1-l00g33k@gmail.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/net/dsa/mv88e6xxx/chip.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c index 8b2c8546f4c99..177151298d72a 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c @@ -2310,6 +2310,14 @@ static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) /* If there is a GPIO connected to the reset pin, toggle it */ if (gpiod) { + /* If the switch has just been reset and not yet completed + * loading EEPROM, the reset may interrupt the I2C transaction + * mid-byte, causing the first EEPROM read after the reset + * from the wrong location resulting in the switch booting + * to wrong mode and inoperable. + */ + mv88e6xxx_g1_wait_eeprom_done(chip); + gpiod_set_value_cansleep(gpiod, 1); usleep_range(10000, 20000); gpiod_set_value_cansleep(gpiod, 0); -- 2.40.1