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From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
To: stable@vger.kernel.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	patches@lists.linux.dev,
	Nathan Chancellor <natechancellor@gmail.com>,
	Ilie Halip <ilie.halip@gmail.com>,
	Michael Ellerman <mpe@ellerman.id.au>,
	Nathan Chancellor <nathan@kernel.org>
Subject: [PATCH 5.4 1/3] powerpc/pmac/smp: Avoid unused-variable warnings
Date: Thu, 31 Aug 2023 13:09:55 +0200	[thread overview]
Message-ID: <20230831110828.935770467@linuxfoundation.org> (raw)
In-Reply-To: <20230831110828.874071888@linuxfoundation.org>

5.4-stable review patch.  If anyone has any objections, please let me know.

------------------

From: Ilie Halip <ilie.halip@gmail.com>

commit 9451c79bc39e610882bdd12370f01af5004a3c4f upstream.

When building with ppc64_defconfig, the compiler reports
that these 2 variables are not used:
    warning: unused variable 'core99_l2_cache' [-Wunused-variable]
    warning: unused variable 'core99_l3_cache' [-Wunused-variable]

They are only used when CONFIG_PPC64 is not defined. Move
them into a section which does the same macro check.

Reported-by: Nathan Chancellor <natechancellor@gmail.com>
Signed-off-by: Ilie Halip <ilie.halip@gmail.com>
[mpe: Move them into core99_init_caches() which is their only user]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20190920153951.25762-1-ilie.halip@gmail.com
Cc: Nathan Chancellor <nathan@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 arch/powerpc/platforms/powermac/smp.c |    8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

--- a/arch/powerpc/platforms/powermac/smp.c
+++ b/arch/powerpc/platforms/powermac/smp.c
@@ -660,13 +660,13 @@ static void smp_core99_gpio_tb_freeze(in
 
 #endif /* !CONFIG_PPC64 */
 
-/* L2 and L3 cache settings to pass from CPU0 to CPU1 on G4 cpus */
-volatile static long int core99_l2_cache;
-volatile static long int core99_l3_cache;
-
 static void core99_init_caches(int cpu)
 {
 #ifndef CONFIG_PPC64
+	/* L2 and L3 cache settings to pass from CPU0 to CPU1 on G4 cpus */
+	volatile static long int core99_l2_cache;
+	volatile static long int core99_l3_cache;
+
 	if (!cpu_has_feature(CPU_FTR_L2CR))
 		return;
 



  reply	other threads:[~2023-08-31 11:10 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-08-31 11:09 [PATCH 5.4 0/3] 5.4.256-rc1 review Greg Kroah-Hartman
2023-08-31 11:09 ` Greg Kroah-Hartman [this message]
2023-08-31 11:09 ` [PATCH 5.4 2/3] powerpc/pmac/smp: Drop unnecessary volatile qualifier Greg Kroah-Hartman
2023-08-31 11:09 ` [PATCH 5.4 3/3] Revert "MIPS: Alchemy: fix dbdma2" Greg Kroah-Hartman
2023-08-31 18:56 ` [PATCH 5.4 0/3] 5.4.256-rc1 review Florian Fainelli
2023-09-01  9:20 ` Sudip Mukherjee (Codethink)
2023-09-01 12:48 ` Naresh Kamboju
2023-09-01 15:57 ` Shuah Khan
2023-09-01 18:39 ` Jon Hunter
2023-09-02  4:17 ` Guenter Roeck

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