From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 41F041D523 for ; Wed, 4 Oct 2023 18:04:01 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id BA90CC433C8; Wed, 4 Oct 2023 18:04:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1696442641; bh=a1/tr3Pk37rvh5cPIeyPtT4+4Q353Sscg8ZpgQMhAGw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=k5U2tZziPuqYOo1mDQPG4LmdIA2Ay48sLWZAXT7+QIP9MqF5O8PRlbGdayLE4S6om 7EMktryv7/wv6Y6GhhxKmd82WlcJX50ruaLU3CWHTc8xFfp0Lh3X1UlBl0bfo0pDkz WJ1eHzB/ibiNAyL9Nx9TDDnk+uJYhbPd0WvlOXkI= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Jie Wang , Jijie Shao , Paolo Abeni , Sasha Levin Subject: [PATCH 5.15 057/183] net: hns3: add 5ms delay before clear firmware reset irq source Date: Wed, 4 Oct 2023 19:54:48 +0200 Message-ID: <20231004175206.306592342@linuxfoundation.org> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231004175203.943277832@linuxfoundation.org> References: <20231004175203.943277832@linuxfoundation.org> User-Agent: quilt/0.67 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 5.15-stable review patch. If anyone has any objections, please let me know. ------------------ From: Jie Wang [ Upstream commit 0770063096d5da4a8e467b6e73c1646a75589628 ] Currently the reset process in hns3 and firmware watchdog init process is asynchronous. we think firmware watchdog initialization is completed before hns3 clear the firmware interrupt source. However, firmware initialization may not complete early. so we add delay before hns3 clear firmware interrupt source and 5 ms delay is enough to avoid second firmware reset interrupt. Fixes: c1a81619d73a ("net: hns3: Add mailbox interrupt handling to PF driver") Signed-off-by: Jie Wang Signed-off-by: Jijie Shao Signed-off-by: Paolo Abeni Signed-off-by: Sasha Levin --- drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c index 0f522daf8e3ab..ca59e1cd992e5 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c @@ -3391,9 +3391,14 @@ static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval) static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type, u32 regclr) { +#define HCLGE_IMP_RESET_DELAY 5 + switch (event_type) { case HCLGE_VECTOR0_EVENT_PTP: case HCLGE_VECTOR0_EVENT_RST: + if (regclr == BIT(HCLGE_VECTOR0_IMPRESET_INT_B)) + mdelay(HCLGE_IMP_RESET_DELAY); + hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr); break; case HCLGE_VECTOR0_EVENT_MBX: -- 2.40.1