Re: [PATCH v5 00/27] Update SMMUv3 to the modern iommu API (part 2/3)

[Jason Gunthorpe <jgg@nvidia.com>]

On Sat, Mar 23, 2024 at 01:38:04PM +0000, Mostafa Saleh wrote:
> Hi Jason,
> 
> On Mon, Mar 04, 2024 at 07:43:48PM -0400, Jason Gunthorpe wrote:
> > Continuing the work of part 1 this focuses on the CD, PASID and SVA
> > components:
> > 
> >  - attach_dev failure does not change the HW configuration.
> > 
> >  - Full PASID API support including:
> >     - S1/SVA domains attached to PASIDs
> 
> I am still going through the series, but I see at the end the main SMMUv3
> driver has set_dev_pasid operation, are there any in-tree drivers that
> use that? (and how can I test it).

Not yet, but some will be coming. Currently only Intel driver supports
it, but Intel HW has other problems making it unusable..

A big part of the effort here is to enable the platform ecosystem so
devices and drivers can use it.  Moritz has access to a device that
can exercise this, though we are still working on it.

> >     - IDENTITY/BLOCKED/S1 attached to RID
> >     - Change of the RID domain while PASIDs are attached
> > 
> >  - Streamlined SVA support using the core infrastructure
> > 
> >  - Hitless, whenever possible, change between two domains
> 
> Can you please clarify what cases are expected to be hitless?
> From what I see if ASID and TTB0 changes that would break the CD.

Right. For CD it is only the SVA mm release flow, setting EPD0.

Jason