From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 97BC4181D19 for ; Wed, 24 Apr 2024 18:15:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982526; cv=none; b=mgBU3TIvYhiIlpr2n1EvM4VPJ/2P2k60yr/lt/nlAdwi0DO8Ud853oZu7hXP2r/kyNnNKb/OCuvmJ7Z28wFkPO6azvmcaBCAa0omn2glpEKxh89sAms67SFEHLd38uyf1oBtdLYSfUN9smNQKdmoufglMWIFP0j882E/fMcvHmk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1713982526; c=relaxed/simple; bh=AsjGODFPSGB1rd7KGy1xLTYIPWqwB7V2MxUYDxCtEt0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Sgjm/m6X3hbAscWsemBaey0XULMe1eGNsCgcl0T0DAOPgC1PXHNN827BEs4IEtocvT8yRfA9Mu9IXz+SMFd2ZSrctOUIuQQqAJdSlUtI2rgl0A6pUl1Nq6Yd1YqvZcx2trl6qyGsJgIQy5dWw2/tI12ZMFSD2RxbpIB9jrN4sdI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=IYiWZvKz; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="IYiWZvKz" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1713982524; x=1745518524; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=AsjGODFPSGB1rd7KGy1xLTYIPWqwB7V2MxUYDxCtEt0=; b=IYiWZvKzBOAUOHF5ZUm3h8RTqFyA2h3GcZ5BoFp/v5tldxcpl8UfXqCm yYLbbhhOVdo9OiUQ8yzo0T4segIJYlpAbYeocLiPdo54rk2l278zJJ1U1 OiDLrFsuthAeSJwVSFQaIvEbqddiMT6QAagtCcdqej9ToG55BWglZiW9p fVloby0zXqyCf+ab7nX6sa/eKpX9iSDNZn5Gyh1OeIH3aVQoPPiJgF/tn iLk0wsqMndzeS4cokcsYjjC+ojXppuKEC6T/1c4ExqQCpqf/CBUFHNs0c I5shCsB29aHkkt0QJycCC2dOdQ7twPtWZV5nnKxopbqG7RzU5UrD/N9g+ w==; X-CSE-ConnectionGUID: pNoJvSAcS0uV3oYiWC+oGA== X-CSE-MsgGUID: TRhi4jpyQoqFcPchscfHew== X-IronPort-AV: E=McAfee;i="6600,9927,11054"; a="9482040" X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="9482040" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:15 -0700 X-CSE-ConnectionGUID: K3hFkVG1Sseq0SnQKXWUCg== X-CSE-MsgGUID: +9Cg8+tzTJO+K/x3MGB3aw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,226,1708416000"; d="scan'208";a="29262772" Received: from agluck-desk3.sc.intel.com ([172.25.222.105]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Apr 2024 11:15:15 -0700 From: Tony Luck To: Borislav Petkov , Thomas Gleixner , Ingo Molnar , Dave Hansen , x86@kernel.org Cc: Fenghua Yu , Reinette Chatre , "H. Peter Anvin" , linux-kernel@vger.kernel.org, patches@lists.linux.dev, Tony Luck Subject: [PATCH v4 37/71] x86/resctrl: Switch to new Intel CPU model defines Date: Wed, 24 Apr 2024 11:15:14 -0700 Message-ID: <20240424181514.41867-1-tony.luck@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240424181245.41141-1-tony.luck@intel.com> References: <20240424181245.41141-1-tony.luck@intel.com> Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit New CPU #defines encode vendor and family as well as model. Signed-off-by: Tony Luck --- arch/x86/kernel/cpu/resctrl/pseudo_lock.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c index 884b88e25141..04584a76ceb4 100644 --- a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c +++ b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c @@ -23,7 +23,7 @@ #include #include -#include +#include #include #include @@ -88,8 +88,8 @@ static u64 get_prefetch_disable_bits(void) boot_cpu_data.x86 != 6) return 0; - switch (boot_cpu_data.x86_model) { - case INTEL_FAM6_BROADWELL_X: + switch (boot_cpu_data.x86_vfm) { + case INTEL_BROADWELL_X: /* * SDM defines bits of MSR_MISC_FEATURE_CONTROL register * as: @@ -100,8 +100,8 @@ static u64 get_prefetch_disable_bits(void) * 63:4 Reserved */ return 0xF; - case INTEL_FAM6_ATOM_GOLDMONT: - case INTEL_FAM6_ATOM_GOLDMONT_PLUS: + case INTEL_ATOM_GOLDMONT: + case INTEL_ATOM_GOLDMONT_PLUS: /* * SDM defines bits of MSR_MISC_FEATURE_CONTROL register * as: @@ -1084,9 +1084,9 @@ static int measure_l2_residency(void *_plr) * L2_HIT 02H * L2_MISS 10H */ - switch (boot_cpu_data.x86_model) { - case INTEL_FAM6_ATOM_GOLDMONT: - case INTEL_FAM6_ATOM_GOLDMONT_PLUS: + switch (boot_cpu_data.x86_vfm) { + case INTEL_ATOM_GOLDMONT: + case INTEL_ATOM_GOLDMONT_PLUS: perf_miss_attr.config = X86_CONFIG(.event = 0xd1, .umask = 0x10); perf_hit_attr.config = X86_CONFIG(.event = 0xd1, @@ -1123,8 +1123,8 @@ static int measure_l3_residency(void *_plr) * MISS 41H */ - switch (boot_cpu_data.x86_model) { - case INTEL_FAM6_BROADWELL_X: + switch (boot_cpu_data.x86_vfm) { + case INTEL_BROADWELL_X: /* On BDW the hit event counts references, not hits */ perf_hit_attr.config = X86_CONFIG(.event = 0x2e, .umask = 0x4f); @@ -1142,7 +1142,7 @@ static int measure_l3_residency(void *_plr) */ counts.miss_after -= counts.miss_before; - if (boot_cpu_data.x86_model == INTEL_FAM6_BROADWELL_X) { + if (boot_cpu_data.x86_vfm == INTEL_BROADWELL_X) { /* * On BDW references and misses are counted, need to adjust. * Sometimes the "hits" counter is a bit more than the -- 2.44.0