From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D1EB211C; Tue, 30 Apr 2024 11:16:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714475768; cv=none; b=KNm2uhsMtiHNChkDCgHwc5eoV9+aIB/fuuo5kJWI4C20geNIDMwFICQCk6+G0Uybmb5iNPQx1wZF5IDT3k1Z2oLpD1r6ZyhaNOQlbP8g7lmo5HlzyK+YAJHqUQmxFO3/S1hRIvsIW7oUxuRzATraYj4egmwwikr9V1yWn18GU0I= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714475768; c=relaxed/simple; bh=f1r36kzcRmiIcvPbiAWjd03LlFUn+u2XS0nbCJa5HJ0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=M+ggBJ0+fSBrJWmP8XENmIBR7+Wyfu/rPzm+SnDwqo9sHoCovBJLQRmoYNUTU0uNWi6od2X9kJiRZm1Fw0nQHpmkUDahO9BCu8B+V0hZZOY64sBOm6ZlPojGY5JPBtfii2twmFts3vo/7tpRuUP0cd0E5G7p9UFJUPnJjzKKhxg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=CumSNnpD; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="CumSNnpD" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BF8EBC4AF18; Tue, 30 Apr 2024 11:16:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1714475768; bh=f1r36kzcRmiIcvPbiAWjd03LlFUn+u2XS0nbCJa5HJ0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CumSNnpD7s0kqSaaNJsV7KndwQobzpGC1UYeM+wj/9DdmigHM0Kcs+57fzsPV4EPk pSfhGOCAmQbFXJwuQf3yh/v+zIWp/RjApcVb0H4nwma79xlCsQU/eeAb38Pxk5FjQ+ hhBdD4HU3ArZsXRUES10PhO0jVDYs4X9obhtwcF8= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= , AngeloGioacchino Del Regno , Sasha Levin Subject: [PATCH 5.15 12/80] arm64: dts: mediatek: mt7622: fix clock controllers Date: Tue, 30 Apr 2024 12:39:44 +0200 Message-ID: <20240430103043.774603252@linuxfoundation.org> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240430103043.397234724@linuxfoundation.org> References: <20240430103043.397234724@linuxfoundation.org> User-Agent: quilt/0.67 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 5.15-stable review patch. If anyone has any objections, please let me know. ------------------ From: Rafał Miłecki [ Upstream commit 3ba5a61594347ab46e7c2cff6cd63ea0f1282efb ] 1. Drop unneeded "syscon"s (bindings were updated recently) 2. Use "clock-controller" in nodenames 3. Add missing "#clock-cells" Fixes: d7167881e03e ("arm64: dts: mt7622: add clock controller device nodes") Fixes: e9b65ecb7c30 ("arm64: dts: mediatek: mt7622: introduce nodes for Wireless Ethernet Dispatch") Signed-off-by: Rafał Miłecki Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240317221050.18595-2-zajec5@gmail.com Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Sasha Levin --- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 27 +++++++++++------------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi index 636783511779a..a5395d1d098c0 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -275,16 +275,14 @@ }; }; - apmixedsys: apmixedsys@10209000 { - compatible = "mediatek,mt7622-apmixedsys", - "syscon"; + apmixedsys: clock-controller@10209000 { + compatible = "mediatek,mt7622-apmixedsys"; reg = <0 0x10209000 0 0x1000>; #clock-cells = <1>; }; - topckgen: topckgen@10210000 { - compatible = "mediatek,mt7622-topckgen", - "syscon"; + topckgen: clock-controller@10210000 { + compatible = "mediatek,mt7622-topckgen"; reg = <0 0x10210000 0 0x1000>; #clock-cells = <1>; }; @@ -715,9 +713,8 @@ power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>; }; - ssusbsys: ssusbsys@1a000000 { - compatible = "mediatek,mt7622-ssusbsys", - "syscon"; + ssusbsys: clock-controller@1a000000 { + compatible = "mediatek,mt7622-ssusbsys"; reg = <0 0x1a000000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; @@ -774,9 +771,8 @@ }; }; - pciesys: pciesys@1a100800 { - compatible = "mediatek,mt7622-pciesys", - "syscon"; + pciesys: clock-controller@1a100800 { + compatible = "mediatek,mt7622-pciesys"; reg = <0 0x1a100800 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; @@ -894,12 +890,13 @@ }; }; - hifsys: syscon@1af00000 { - compatible = "mediatek,mt7622-hifsys", "syscon"; + hifsys: clock-controller@1af00000 { + compatible = "mediatek,mt7622-hifsys"; reg = <0 0x1af00000 0 0x70>; + #clock-cells = <1>; }; - ethsys: syscon@1b000000 { + ethsys: clock-controller@1b000000 { compatible = "mediatek,mt7622-ethsys", "syscon"; reg = <0 0x1b000000 0 0x1000>; -- 2.43.0