* [PATCH] Documentation/x86: Switch to new Intel CPU model defines
@ 2024-06-11 20:48 Tony Luck
2024-06-17 22:28 ` Jonathan Corbet
0 siblings, 1 reply; 2+ messages in thread
From: Tony Luck @ 2024-06-11 20:48 UTC (permalink / raw)
To: Jonathan Corbet; +Cc: x86, linux-kernel, linux-doc, patches, Tony Luck
New CPU #defines encode vendor and family as well as model
so "_FAM6" is no longer used in the #define names.
Signed-off-by: Tony Luck <tony.luck@intel.com>
---
Documentation/arch/x86/cpuinfo.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/arch/x86/cpuinfo.rst b/Documentation/arch/x86/cpuinfo.rst
index 8895784d4784..6ef426a52cdc 100644
--- a/Documentation/arch/x86/cpuinfo.rst
+++ b/Documentation/arch/x86/cpuinfo.rst
@@ -112,7 +112,7 @@ conditions are met, the features are enabled by the set_cpu_cap or
setup_force_cpu_cap macros. For example, if bit 5 is set in MSR_IA32_CORE_CAPS,
the feature X86_FEATURE_SPLIT_LOCK_DETECT will be enabled and
"split_lock_detect" will be displayed. The flag "ring3mwait" will be
-displayed only when running on INTEL_FAM6_XEON_PHI_[KNL|KNM] processors.
+displayed only when running on INTEL_XEON_PHI_[KNL|KNM] processors.
d: Flags can represent purely software features.
------------------------------------------------
--
2.45.0
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] Documentation/x86: Switch to new Intel CPU model defines
2024-06-11 20:48 [PATCH] Documentation/x86: Switch to new Intel CPU model defines Tony Luck
@ 2024-06-17 22:28 ` Jonathan Corbet
0 siblings, 0 replies; 2+ messages in thread
From: Jonathan Corbet @ 2024-06-17 22:28 UTC (permalink / raw)
To: Tony Luck; +Cc: x86, linux-kernel, linux-doc, patches, Tony Luck
Tony Luck <tony.luck@intel.com> writes:
> New CPU #defines encode vendor and family as well as model
> so "_FAM6" is no longer used in the #define names.
>
> Signed-off-by: Tony Luck <tony.luck@intel.com>
> ---
> Documentation/arch/x86/cpuinfo.rst | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/arch/x86/cpuinfo.rst b/Documentation/arch/x86/cpuinfo.rst
> index 8895784d4784..6ef426a52cdc 100644
> --- a/Documentation/arch/x86/cpuinfo.rst
> +++ b/Documentation/arch/x86/cpuinfo.rst
> @@ -112,7 +112,7 @@ conditions are met, the features are enabled by the set_cpu_cap or
> setup_force_cpu_cap macros. For example, if bit 5 is set in MSR_IA32_CORE_CAPS,
> the feature X86_FEATURE_SPLIT_LOCK_DETECT will be enabled and
> "split_lock_detect" will be displayed. The flag "ring3mwait" will be
> -displayed only when running on INTEL_FAM6_XEON_PHI_[KNL|KNM] processors.
> +displayed only when running on INTEL_XEON_PHI_[KNL|KNM] processors.
>
Applied, thanks.
jon
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2024-06-17 22:28 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-06-11 20:48 [PATCH] Documentation/x86: Switch to new Intel CPU model defines Tony Luck
2024-06-17 22:28 ` Jonathan Corbet
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).