From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5CF1418E05E; Tue, 30 Jul 2024 16:11:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722355863; cv=none; b=JFXpfpjdgZo4CKpHp5ZVqWeSnZqADBMSCAXVQ5QIaKrDDj6ACxQVD1BCrYDyDcKMQ5NHdXFELX3w8+sb+kqLrzJpKza4Xx/vDlJNTli2aYA/3jyX5V4zwhClvppSA3p1IEFT6Jc7RA5naUL625Fw4wIMtLoKq7IB7Lnp1YsjOss= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722355863; c=relaxed/simple; bh=+WnnGaBnhFlE7MpsbfgMpzxlf1Yc3vQ2UcuUf2K4mf0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kwnXww9XR/wMVgQHx1WH1v8GHanyjK5o9ORuhzqo3TWDb9S/Jir+QtYwisTdZEEb0GsxajSwv8HB3tz0/pAtV0sKgtiYjmHYG3VnR1bgQ1TcNpHpgRoxmjysGAlCHsj6mkj3O9PcrDzEVEhCL/vPQy9dohjTW+fZpVKddwH0ogY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=dw7R3bgM; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="dw7R3bgM" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 80BB3C32782; Tue, 30 Jul 2024 16:11:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1722355863; bh=+WnnGaBnhFlE7MpsbfgMpzxlf1Yc3vQ2UcuUf2K4mf0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dw7R3bgMa2x6GQFROW6IF2mEKkuau4Er3hAQRUIdtGi3z5WIC9dsiNwb6AKGoQOUU DYauG8cEX9gMZTANGbAW0rmS1jw/ZAPK31oVV9U6VAMQvk2O6//ukmx21++5qXBMU0 0VCyVkbJgR9GDUzAXgD+htWihntaNY++TZ9wgCAY= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Michael Walle , Shawn Guo , Sasha Levin Subject: [PATCH 6.10 095/809] ARM: dts: imx6qdl-kontron-samx6i: fix PHY reset Date: Tue, 30 Jul 2024 17:39:31 +0200 Message-ID: <20240730151728.388573950@linuxfoundation.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240730151724.637682316@linuxfoundation.org> References: <20240730151724.637682316@linuxfoundation.org> User-Agent: quilt/0.67 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.10-stable review patch. If anyone has any objections, please let me know. ------------------ From: Michael Walle [ Upstream commit edfea889a049abe80f0d55c0365bf60fbade272f ] The PHY reset line is connected to both the SoC (GPIO1_25) and the CPLD. We must not use the GPIO1_25 as it will drive against the output buffer of the CPLD. Instead there is another GPIO (GPIO2_01), an input to the CPLD, which will tell the CPLD to assert the PHY reset line. Fixes: 2a51f9dae13d ("ARM: dts: imx6qdl-kontron-samx6i: Add iMX6-based Kontron SMARC-sAMX6i module") Fixes: 5694eed98cca ("ARM: dts: imx6qdl-kontron-samx6i: move phy reset into phy-node") Signed-off-by: Michael Walle Signed-off-by: Shawn Guo Signed-off-by: Sasha Levin --- arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi index d8c1dfb8c9abb..d6c049b9a9c69 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi @@ -269,7 +269,7 @@ mdio { ethphy: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; - reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; reset-assert-us = <1000>; }; }; @@ -516,7 +516,7 @@ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 /* RST_GBE0_PHY# */ + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 /* RST_GBE0_PHY# */ >; }; -- 2.43.0