From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B3A791A76A5; Tue, 30 Jul 2024 17:31:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722360690; cv=none; b=acbqo65weya7UUqPGwdepPys61IHlPB5P006qyMoFuUjJgZiGKg9JDF39s9RskmPpfT1m7rzgtFML6UdaYP8fP4x3WXP0RiWmKC6Zast+aT5qbcHU0au86ANX829ANbayHHtVnOx0NUJjKNq/qf32vFjYqKqvtFi/M+SKlpycAU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1722360690; c=relaxed/simple; bh=t/se+qdtTrmesEpBszKs4cSrMNYg88t1EVePALpZ6r4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=R2+e+3Tg8Nr9X9G1FW/jPvL4elAV0rCErqpmXtNZsYcdv6oqSbUlXosOEVhR6d9ZcOUaZ92sLEB3PqdTMVF67Yr9ca0kCkN8qjqFYs6SZLalE8vSeuBuN8GZ3vUUHvqfKrgdFTcSK9xs2xjlsQ+juyACmc8cDtfLuZsM7GKlBVk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=oGsHCZJm; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="oGsHCZJm" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3481BC32782; Tue, 30 Jul 2024 17:31:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1722360690; bh=t/se+qdtTrmesEpBszKs4cSrMNYg88t1EVePALpZ6r4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oGsHCZJmy6127LYIuwy9MMIEVhH7R6CJRpZrRhDbeRIntloc1XRDzftCst9oSCb/P 3SBN3LcGtG5tXLQIZAMY2WmIlN+B6jk6cS0CP9ompy2Hvb2wT8k+XolHzMzXkXAmu0 tXSH7XitnbMyPDNh4ZWyRVvMRelv+ZKj9+ZpAVns= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Gregory CLEMENT , Jiaxun Yang , Thomas Bogendoerfer , Sasha Levin Subject: [PATCH 6.10 760/809] MIPS: SMP-CPS: Fix address for GCR_ACCESS register for CM3 and later Date: Tue, 30 Jul 2024 17:50:36 +0200 Message-ID: <20240730151754.979736343@linuxfoundation.org> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240730151724.637682316@linuxfoundation.org> References: <20240730151724.637682316@linuxfoundation.org> User-Agent: quilt/0.67 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.10-stable review patch. If anyone has any objections, please let me know. ------------------ From: Gregory CLEMENT [ Upstream commit a263e5f309f32301e1f3ad113293f4e68a82a646 ] When the CM block migrated from CM2.5 to CM3.0, the address offset for the Global CSR Access Privilege register was modified. We saw this in the "MIPS64 I6500 Multiprocessing System Programmer's Guide," it is stated that "the Global CSR Access Privilege register is located at offset 0x0120" in section 5.4. It is at least the same for I6400. This fix allows to use the VP cores in SMP mode if the reset values were modified by the bootloader. Based on the work of Vladimir Kondratiev and the feedback from Jiaxun Yang . Fixes: 197e89e0984a ("MIPS: mips-cm: Implement mips_cm_revision") Signed-off-by: Gregory CLEMENT Reviewed-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer Signed-off-by: Sasha Levin --- arch/mips/include/asm/mips-cm.h | 4 ++++ arch/mips/kernel/smp-cps.c | 5 ++++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h index c2930a75b7e44..1e782275850a3 100644 --- a/arch/mips/include/asm/mips-cm.h +++ b/arch/mips/include/asm/mips-cm.h @@ -240,6 +240,10 @@ GCR_ACCESSOR_RO(32, 0x0d0, gic_status) GCR_ACCESSOR_RO(32, 0x0f0, cpc_status) #define CM_GCR_CPC_STATUS_EX BIT(0) +/* GCR_ACCESS - Controls core/IOCU access to GCRs */ +GCR_ACCESSOR_RW(32, 0x120, access_cm3) +#define CM_GCR_ACCESS_ACCESSEN GENMASK(7, 0) + /* GCR_L2_CONFIG - Indicates L2 cache configuration when Config5.L2C=1 */ GCR_ACCESSOR_RW(32, 0x130, l2_config) #define CM_GCR_L2_CONFIG_BYPASS BIT(20) diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index 9cc087dd1c194..395622c373258 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -317,7 +317,10 @@ static void boot_core(unsigned int core, unsigned int vpe_id) write_gcr_co_reset_ext_base(CM_GCR_Cx_RESET_EXT_BASE_UEB); /* Ensure the core can access the GCRs */ - set_gcr_access(1 << core); + if (mips_cm_revision() < CM_REV_CM3) + set_gcr_access(1 << core); + else + set_gcr_access_cm3(1 << core); if (mips_cpc_present()) { /* Reset the core */ -- 2.43.0