From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 061B01D0403; Wed, 2 Oct 2024 13:30:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727875830; cv=none; b=XVijN8QhkSXJiaRBZPSqPsJeEHra94JDIiCb6sPCRDp8TSwKA9AKjR8Pt1UoUpmgmtQLR+DGrHyP0pM1pPrtqX77JTq+2DaAoUAV6zSTBySdEdtKz6Zk1udQjyOp/2D3AuZ1PN6VMYQjknVyKX35kGK+s/5IGSr4P0NTabO9VIM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727875830; c=relaxed/simple; bh=QK7OSkAkbAXRdGw6jxTWhRMQkYNk1JTPlK852Bmj3zE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=amuXUuJQXLY5GyRcaIVtM1joXoIa/pRJgjI8cqipYSnXK3QLmT/A/+DmtngIf8C2L6o2/ziP+cKtbT7iQTrWKpvV9j5TTxOKieX/xqlnkJ5UtJktIVvXar33xk7QwFz26xsABXlyY0Z6+raCg+1YQhcsi0l0prBAraEUb2K1OaM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=ooIq56II; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="ooIq56II" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 83BCCC4CEC5; Wed, 2 Oct 2024 13:30:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1727875829; bh=QK7OSkAkbAXRdGw6jxTWhRMQkYNk1JTPlK852Bmj3zE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ooIq56II+/jBOen47rWWQGIUP0e+NVMfVi3J8SghQOPkfev93DSwJ40jxiN+gpD8s AzgUlL2sdsgabwzhSiFAuHisx+kqGyh39ybq/hqPtd/Xhc94IwKpSJ5JnYAxCHlQPB hx4Yt4Jptd7BlnvieLS797c+YgmlfdQK3Vgfs12s= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Dmitry Baryshkov , Abhinav Kumar , Sasha Levin Subject: [PATCH 6.11 236/695] drm/msm/dsi: correct programming sequence for SM8350 / SM8450 Date: Wed, 2 Oct 2024 14:53:54 +0200 Message-ID: <20241002125831.868251481@linuxfoundation.org> X-Mailer: git-send-email 2.46.2 In-Reply-To: <20241002125822.467776898@linuxfoundation.org> References: <20241002125822.467776898@linuxfoundation.org> User-Agent: quilt/0.67 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.11-stable review patch. If anyone has any objections, please let me know. ------------------ From: Dmitry Baryshkov [ Upstream commit 1328cb7c34bf6d056df9ff694ee5194537548258 ] According to the display-drivers, 5nm DSI PLL (v4.2, v4.3) have different boundaries for pll_clock_inverters programming. Follow the vendor code and use correct values. Fixes: 2f9ae4e395ed ("drm/msm/dsi: add support for DSI-PHY on SM8350 and SM8450") Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar Patchwork: https://patchwork.freedesktop.org/patch/606947/ Link: https://lore.kernel.org/r/20240804-sm8350-fixes-v1-3-1149dd8399fe@linaro.org Signed-off-by: Sasha Levin --- drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index 3b59137ca6743..031446c87daec 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -135,7 +135,7 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, struct dsi_pll_config config->pll_clock_inverters = 0x00; else config->pll_clock_inverters = 0x40; - } else { + } else if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { if (pll_freq <= 1000000000ULL) config->pll_clock_inverters = 0xa0; else if (pll_freq <= 2500000000ULL) @@ -144,6 +144,16 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, struct dsi_pll_config config->pll_clock_inverters = 0x00; else config->pll_clock_inverters = 0x40; + } else { + /* 4.2, 4.3 */ + if (pll_freq <= 1000000000ULL) + config->pll_clock_inverters = 0xa0; + else if (pll_freq <= 2500000000ULL) + config->pll_clock_inverters = 0x20; + else if (pll_freq <= 3500000000ULL) + config->pll_clock_inverters = 0x00; + else + config->pll_clock_inverters = 0x40; } config->decimal_div_start = dec; -- 2.43.0