From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 988221D079C; Wed, 2 Oct 2024 13:53:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727877203; cv=none; b=Xg6BKd4GsdcHR9lNgd+0gTiHcA3n1ctwudVrqOZmxcgFPdh6oyY9lb5/b/G59FDANMDttYcVbhDc7dbTaP8xbY1fQjcI33yIdlN8V5Qtk5WhPTHBTUbyk1uPQMIa1E4oYya9vABuLBipaFrSVXzcC2Q6MErlxoE6/jK+IvvyqGQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727877203; c=relaxed/simple; bh=kbeCZC7U+/sl0UnibzzlnlPybhcCaN2k5FJ4+0RumSE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cWXjc/jhsseY5w/YjOXFXuVsrBW3AvEpRkw4xwtk8ilfFGpB4OdOyM8w2BvMHpdKUhc5+xDryOb+lqHobypBKHpZMocPNS9sdPNvs97eruxmnlv3zIhCg1VWVuv5zbvebcagIw5U19BGIRkB05mZ5EOHVgmqsjiIQfjCPadZ/5I= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=h/W0i0Oj; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="h/W0i0Oj" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1FFD2C4CEC2; Wed, 2 Oct 2024 13:53:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1727877203; bh=kbeCZC7U+/sl0UnibzzlnlPybhcCaN2k5FJ4+0RumSE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=h/W0i0OjMCxHjyCiRJJs9+ZEt/HNUo0ijPSCWOnTq+QxHP4hZdN1ApzK3lVR6/wux 0ur7hkuPadhkPjpTNkr91VAeIaj3lxO1ytEQIVhuLVIUrVGS1bnpMOoo36MZm2x7ad 1lH5lRacHq0GYlDw7WVqTRQHBh9v+FjyVH1CSVxM= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Krzysztof Kozlowski , Parthiban Nallathambi , Shawn Guo Subject: [PATCH 6.11 659/695] ARM: dts: imx6ull-seeed-npi: fix fsl,pins property in tscgrp pinctrl Date: Wed, 2 Oct 2024 15:00:57 +0200 Message-ID: <20241002125848.815472557@linuxfoundation.org> X-Mailer: git-send-email 2.46.2 In-Reply-To: <20241002125822.467776898@linuxfoundation.org> References: <20241002125822.467776898@linuxfoundation.org> User-Agent: quilt/0.67 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.11-stable review patch. If anyone has any objections, please let me know. ------------------ From: Krzysztof Kozlowski commit 3dedd4889cfc2851444a1f7626b293c0bfd1e42c upstream. The property is "fsl,pins", not "fsl,pin". Wrong property means the pin configuration was not applied. Fixes dtbs_check warnings: imx6ull-seeed-npi-dev-board-emmc.dtb: pinctrl@20e0000: uart1grp: 'fsl,pins' is a required property imx6ull-seeed-npi-dev-board-emmc.dtb: pinctrl@20e0000: uart1grp: 'fsl,pin' does not match any of the regexes: 'pinctrl-[0-9]+' Cc: stable@vger.kernel.org Fixes: e3b5697195c8 ("ARM: dts: imx6ull: add seeed studio NPi dev board") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Parthiban Nallathambi Signed-off-by: Shawn Guo Signed-off-by: Greg Kroah-Hartman --- arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi-dev-board.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) --- a/arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi-dev-board.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-seeed-npi-dev-board.dtsi @@ -339,14 +339,14 @@ }; pinctrl_uart1: uart1grp { - fsl,pin = < + fsl,pins = < MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 >; }; pinctrl_uart2: uart2grp { - fsl,pin = < + fsl,pins = < MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 @@ -355,7 +355,7 @@ }; pinctrl_uart3: uart3grp { - fsl,pin = < + fsl,pins = < MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1 @@ -364,21 +364,21 @@ }; pinctrl_uart4: uart4grp { - fsl,pin = < + fsl,pins = < MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1 MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1 >; }; pinctrl_uart5: uart5grp { - fsl,pin = < + fsl,pins = < MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1 MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1 >; }; pinctrl_usb_otg1_id: usbotg1idgrp { - fsl,pin = < + fsl,pins = < MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 >; };