From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D9311F5853; Wed, 6 Nov 2024 13:09:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730898573; cv=none; b=GmZbhk7Phq+zbi0yESxDdf+Iwc/UxMynkfbxGuBKOjKVNNvYNjV4l7Dn/HjD50YCthNG0MDHIL9IMtXCgHK3xsPtsMVocvEgjGy/CE6kPRKuLHkq+Gm7Kt2HBewRvRg6qQqLyaxpA1xLNr1o2qxhHXs4G8ZMccX6SY86sNbC2gg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1730898573; c=relaxed/simple; bh=Ls5lzgzb5C/281Z9gsYPZvJwhodMqL0jNaYi0qJ7UHs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kecbXknTUCUgE1itr8FHcfGqmMbj2Qx10CIwyTSlprhJpeTShpgA4cs1vim0lzY64hMwTvzVXLGCiKI+fACT/whelmuhBJwjYcaBGOApMtA3ef59XOI0AvpnbgY5xvKNnqfYYKReRtuG7EsROqjpI1NjLJcnj5eQDKcJ4jpZoac= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=x5xuOvhQ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="x5xuOvhQ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C9B98C4CECD; Wed, 6 Nov 2024 13:09:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1730898573; bh=Ls5lzgzb5C/281Z9gsYPZvJwhodMqL0jNaYi0qJ7UHs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=x5xuOvhQm2PuPYgfmm8LblTO2MojwJN09Hka6EHPfIGVy774UzWVJ0NyVathUFDeX hidAEm71xpAqVtrJrFBhqpZL666I1DRkpJ5Hx2s3SB5DGLlcdO5nDBaFjlk8ESTJck jZxLX3Ol5UXzljxL9+k86Yarz+yLWnlzJrkk47S8= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Mark Rutland , James Morse , Will Deacon , Catalin Marinas , Sasha Levin Subject: [PATCH 5.4 284/462] arm64: cputype: Add Neoverse-N3 definitions Date: Wed, 6 Nov 2024 13:02:57 +0100 Message-ID: <20241106120338.537837323@linuxfoundation.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241106120331.497003148@linuxfoundation.org> References: <20241106120331.497003148@linuxfoundation.org> User-Agent: quilt/0.67 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 5.4-stable review patch. If anyone has any objections, please let me know. ------------------ From: Mark Rutland [ Upstream commit 924725707d80bc2588cefafef76ff3f164d299bc ] Add cputype definitions for Neoverse-N3. These will be used for errata detection in subsequent patches. These values can be found in Table A-261 ("MIDR_EL1 bit descriptions") in issue 02 of the Neoverse-N3 TRM, which can be found at: https://developer.arm.com/documentation/107997/0000/?lang=en Signed-off-by: Mark Rutland Cc: James Morse Cc: Will Deacon Link: https://lore.kernel.org/r/20240930111705.3352047-2-mark.rutland@arm.com Signed-off-by: Catalin Marinas [ Mark: trivial backport ] Signed-off-by: Mark Rutland Signed-off-by: Sasha Levin --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index cf5636e5c6c8b..bd2c9057fba9c 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -89,6 +89,7 @@ #define ARM_CPU_PART_NEOVERSE_V3 0xD84 #define ARM_CPU_PART_CORTEX_X925 0xD85 #define ARM_CPU_PART_CORTEX_A725 0xD87 +#define ARM_CPU_PART_NEOVERSE_N3 0xD8E #define APM_CPU_PART_POTENZA 0x000 @@ -139,6 +140,7 @@ #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3) #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925) #define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725) +#define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N3) #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) -- 2.43.0