From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5BC4E2BB1B; Fri, 15 Nov 2024 06:59:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731653981; cv=none; b=EIIr/MwIrIJd+DSMWlPfDrh5V8VDg7utrjdyxamC9YK1O8w7tqJbdlp+8aw/DXlDuXSJzINrazUVBDZAGKfXJ+VdiFBDcG3IRGzhpcXteXHChZ9idRE85g4CpPlMU/p+OdEa+6w5+kPw1vUUgDWAJX3pR/ysyDxXE+UILSp4QG8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731653981; c=relaxed/simple; bh=mUoEAQ6VNO5a7yxkYQhj9g9s6WesLu0WltGMsWLRg5s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rH6uRWv4nBWFCDNEJxlV+OAM/ovLeaaEYPTQHgs1CjPyAitz91QmuyRGEmGICTgEsYiKbV9mER2Wwx9VbitDIfKWVzWL5ZjSpzgOwL4Zsd+IySRkxzdq+NAeJ77qL/FrgeWz5q+oJ+l1emJLONCwoB2Wv/7NMCS9UQP/+0nYAA4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=mVk60Mbs; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="mVk60Mbs" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BF0E6C4CED4; Fri, 15 Nov 2024 06:59:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1731653981; bh=mUoEAQ6VNO5a7yxkYQhj9g9s6WesLu0WltGMsWLRg5s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mVk60MbsDueB9UNWyzS1EGOiCzwYASv5ezTzQcC6p2OOOB73rNI4GeDCYi0K64Pbw ZETly1QwdqvokRfbvRHZiWv66AuzIbApeEGMBRnCXz7vz5XK033YKUd7FSRyJS5nW7 ILfTMq1X5gbEmhde/CA7x/uhd4hQpxR0uJyr1eNA= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Sergey Matsievskiy , Thomas Gleixner , Sasha Levin Subject: [PATCH 5.15 02/22] irqchip/ocelot: Fix trigger register address Date: Fri, 15 Nov 2024 07:38:48 +0100 Message-ID: <20241115063721.263282597@linuxfoundation.org> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241115063721.172791419@linuxfoundation.org> References: <20241115063721.172791419@linuxfoundation.org> User-Agent: quilt/0.67 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 5.15-stable review patch. If anyone has any objections, please let me know. ------------------ From: Sergey Matsievskiy [ Upstream commit 9e9c4666abb5bb444dac37e2d7eb5250c8d52a45 ] Controllers, supported by this driver, have two sets of registers: * (main) interrupt registers control peripheral interrupt sources. * device interrupt registers configure per-device (network interface) interrupts and act as an extra stage before the main interrupt registers. In the driver unmask code, device trigger registers are used in the mask calculation of the main interrupt sticky register, mixing two kinds of registers. Use the main interrupt trigger register instead. Signed-off-by: Sergey Matsievskiy Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/all/20240925184416.54204-2-matsievskiysv@gmail.com Signed-off-by: Sasha Levin --- drivers/irqchip/irq-mscc-ocelot.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-mscc-ocelot.c b/drivers/irqchip/irq-mscc-ocelot.c index 4d0c3532dbe73..c19ab379e8c5e 100644 --- a/drivers/irqchip/irq-mscc-ocelot.c +++ b/drivers/irqchip/irq-mscc-ocelot.c @@ -37,7 +37,7 @@ static struct chip_props ocelot_props = { .reg_off_ena_clr = 0x1c, .reg_off_ena_set = 0x20, .reg_off_ident = 0x38, - .reg_off_trigger = 0x5c, + .reg_off_trigger = 0x4, .n_irq = 24, }; @@ -70,7 +70,7 @@ static struct chip_props jaguar2_props = { .reg_off_ena_clr = 0x1c, .reg_off_ena_set = 0x20, .reg_off_ident = 0x38, - .reg_off_trigger = 0x5c, + .reg_off_trigger = 0x4, .n_irq = 29, }; -- 2.43.0