From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 969EE24889B; Tue, 29 Apr 2025 17:12:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745946756; cv=none; b=NL8nTAv6LuATXZfszKbux177+Pfo6pYXZU2lrh9cJdhCTbLw1JnMZpkzB+xz6v0IExRLMz3A+E47/a1JD1pd1REvyLU5Cv8l909e4NYwRgqAeGO6O1Ea+Sx5ZY7GwQicvozErk2apfw4SS37X3+691gvf1SCQ7mhVZxQlNcARxE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745946756; c=relaxed/simple; bh=AZateUT68CPhjS+kGwBsC+n7aawAXByHFaY2PYK422Y=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Z1S/R/JDAJCye5XiMaE/r66/g/FVtDNw39OeDc/sdipaS4m3Zwm55d49wtdWACpfHkRDaKub6r2ZuHAe6inXz2Bfddhhs58vQoH0OrEvdzT6EAadI10IXikz20AGqeH7/npdw718KdKQ9Y10O2lb+kx/i/xoseXVIC8/iVCXUGw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=opRbe4gJ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="opRbe4gJ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2300EC4CEE3; Tue, 29 Apr 2025 17:12:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1745946756; bh=AZateUT68CPhjS+kGwBsC+n7aawAXByHFaY2PYK422Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=opRbe4gJTYdmsPcKmbVK8st0teKV+MJ0g0C+TxbEaNSq5iEEkVAZSOFIqQKFNOkvt DpRE+zt8OErL6iiRNYbmsOvAvcZewA2EtuD9EIjzTtAHqyMHk/rQYwL6ZtJNW2c0KI mLNMcAktHwUmia71A9H86/oTuQIZE+IGuekF4LMU= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Douglas Anderson , Catalin Marinas Subject: [PATCH 5.10 059/286] arm64: cputype: Add MIDR_CORTEX_A76AE Date: Tue, 29 Apr 2025 18:39:23 +0200 Message-ID: <20250429161110.274553362@linuxfoundation.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250429161107.848008295@linuxfoundation.org> References: <20250429161107.848008295@linuxfoundation.org> User-Agent: quilt/0.68 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 5.10-stable review patch. If anyone has any objections, please let me know. ------------------ From: Douglas Anderson commit a9b5bd81b294d30a747edd125e9f6aef2def7c79 upstream. >>From the TRM, MIDR_CORTEX_A76AE has a partnum of 0xDOE and an implementor of 0x41 (ARM). Add the values. Cc: stable@vger.kernel.org # dependency of the next fix in the series Signed-off-by: Douglas Anderson Link: https://lore.kernel.org/r/20250107120555.v4.4.I151f3b7ee323bcc3082179b8c60c3cd03308aa94@changeid Signed-off-by: Catalin Marinas Signed-off-by: Greg Kroah-Hartman --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -74,6 +74,7 @@ #define ARM_CPU_PART_CORTEX_A76 0xD0B #define ARM_CPU_PART_NEOVERSE_N1 0xD0C #define ARM_CPU_PART_CORTEX_A77 0xD0D +#define ARM_CPU_PART_CORTEX_A76AE 0xD0E #define ARM_CPU_PART_NEOVERSE_V1 0xD40 #define ARM_CPU_PART_CORTEX_A78 0xD41 #define ARM_CPU_PART_CORTEX_A78AE 0xD42 @@ -137,6 +138,7 @@ #define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76) #define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1) #define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77) +#define MIDR_CORTEX_A76AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76AE) #define MIDR_NEOVERSE_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V1) #define MIDR_CORTEX_A78 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78) #define MIDR_CORTEX_A78AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78AE)