From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED9F6297120; Mon, 12 May 2025 18:11:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747073461; cv=none; b=eCm3Q/OHUCpA/DbNZO7Cg+92FYFbEeQG4OCqghbM2jo2qHjrR/XfCEHDO11d6fLrxfUxXnx2CN7oKHsF78NUO4hFTFGb/j8Avr1tsql9Xn/KLTZCRKv2YlzliApH17rT8MxsXasIv0GhyQTMcqDbV39+/v/nHcssEO9eTb7Tkrk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747073461; c=relaxed/simple; bh=U6rrONm87BwbtyqxKz0HZ6j83ME568Cu2wuq3zQWDLM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nvsJPY1sCIUAEb1j2v3TWlnfx/wyJsZnF6yxP52BYSltQjpFT7Ww0rQY4A37JFOqMyS/KKBXoM/RBmKcv5I+QwlwHGOAyt/nonyVDc/xRXxkT5B+44TfqVzA/gHsyN7YRdNFi18Os9hTQRqROn8J3BRlaDri6IZWe57qMD3qptQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=i8QOQtdr; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="i8QOQtdr" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7D126C4CEE7; Mon, 12 May 2025 18:11:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1747073460; bh=U6rrONm87BwbtyqxKz0HZ6j83ME568Cu2wuq3zQWDLM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=i8QOQtdrpKnfBF80IGNODYQam5wHg67U9oyBbKITnO0duhv4Y+sq1NBw4ldY0d6Al 8bGYyAjWxEm2205DZ13qFACpCiG8Dcfj/NcfKHfl+1z1lFtQ4WNUk8YVhRyu6mmgEf 1QcopE+q85ctfxllZX2qdbQD2KeW79wHQi3slG5k= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Alexey Klimov , Felix Kuehling , Alex Deucher Subject: [PATCH 6.6 053/113] drm/amdgpu/hdp4: use memcfg register to post the write for HDP flush Date: Mon, 12 May 2025 19:45:42 +0200 Message-ID: <20250512172029.827293130@linuxfoundation.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250512172027.691520737@linuxfoundation.org> References: <20250512172027.691520737@linuxfoundation.org> User-Agent: quilt/0.68 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.6-stable review patch. If anyone has any objections, please let me know. ------------------ From: Alex Deucher commit f690e3974755a650259a45d71456decc9c96a282 upstream. Reading back the remapped HDP flush register seems to cause problems on some platforms. All we need is a read, so read back the memcfg register. Fixes: c9b8dcabb52a ("drm/amdgpu/hdp4.0: do a posting read when flushing HDP") Reported-by: Alexey Klimov Link: https://lists.freedesktop.org/archives/amd-gfx/2025-April/123150.html Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4119 Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3908 Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher (cherry picked from commit 5c937b4a6050316af37ef214825b6340b5e9e391) Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) --- a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c @@ -42,7 +42,12 @@ static void hdp_v4_0_flush_hdp(struct am { if (!ring || !ring->funcs->emit_wreg) { WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); - RREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2); + /* We just need to read back a register to post the write. + * Reading back the remapped register causes problems on + * some platforms so just read back the memory size register. + */ + if (adev->nbio.funcs->get_memsize) + adev->nbio.funcs->get_memsize(adev); } else { amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); }