From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1826129712B; Mon, 12 May 2025 18:11:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747073516; cv=none; b=oQQ/rC9u3GTUHqtM42818p+5LCNDQCTUuf2DknXKL7UKPse1KpBulH9LzYEinlTyflHu62FB/2r5hBeMNWU8tthbE27vhyHfD8la5WhaIQRy6Ww24QnUHV8OehDRDxWTVjMJyXbRPgQP1RadUHQ0xi4Vawax/NvuTkaD80YeBwo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747073516; c=relaxed/simple; bh=UZoMN9mYEAW2sl5gTU0tLA9eH6u48xrEll8DMr0QiQY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bgcIa8xZsh7lcgiW2V2NiNU5CWltBINGtLLoRcUpd1TNkwbhMWT3ic+3jm/8pByro4eE0AJQe8r8d5l5/Lqlb/hGnfhqB+rpGjVUMW5TcS6oayqn++iZ3K/8S8Xga9oj++FcsqMxVaiPM7v4dJOWS9T8NGxtZz2ktp9YZpydUus= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=lelJhWQh; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="lelJhWQh" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 16B94C4CEE7; Mon, 12 May 2025 18:11:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1747073515; bh=UZoMN9mYEAW2sl5gTU0tLA9eH6u48xrEll8DMr0QiQY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lelJhWQhg1uwuswpnpdEhJaZqA86qFsofBjcsz3Yqr6sjWapTObLGMkzpWyqvarvJ 9YLXUusZptTQBvzv+jsjW20B7z0rWW0pLm8fhFed5UVhkfTD2fa7Zu+0KMRS6d9JGb C48UF2GpUsDQnxLCIrU6eF9qFf+Akr7N3MM7dM+E= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Josh Poimboeuf , Pawan Gupta , Dave Hansen , Alexandre Chartre Subject: [PATCH 6.6 100/113] x86/bhi: Do not set BHI_DIS_S in 32-bit mode Date: Mon, 12 May 2025 19:46:29 +0200 Message-ID: <20250512172031.743134714@linuxfoundation.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250512172027.691520737@linuxfoundation.org> References: <20250512172027.691520737@linuxfoundation.org> User-Agent: quilt/0.68 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.6-stable review patch. If anyone has any objections, please let me know. ------------------ From: Pawan Gupta commit 073fdbe02c69c43fb7c0d547ec265c7747d4a646 upstream. With the possibility of intra-mode BHI via cBPF, complete mitigation for BHI is to use IBHF (history fence) instruction with BHI_DIS_S set. Since this new instruction is only available in 64-bit mode, setting BHI_DIS_S in 32-bit mode is only a partial mitigation. Do not set BHI_DIS_S in 32-bit mode so as to avoid reporting misleading mitigated status. With this change IBHF won't be used in 32-bit mode, also remove the CONFIG_X86_64 check from emit_spectre_bhb_barrier(). Suggested-by: Josh Poimboeuf Signed-off-by: Pawan Gupta Signed-off-by: Dave Hansen Reviewed-by: Josh Poimboeuf Reviewed-by: Alexandre Chartre Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/cpu/bugs.c | 5 +++-- arch/x86/net/bpf_jit_comp.c | 5 +++-- 2 files changed, 6 insertions(+), 4 deletions(-) --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -1677,10 +1677,11 @@ static void __init bhi_select_mitigation return; } - if (spec_ctrl_bhi_dis()) + if (!IS_ENABLED(CONFIG_X86_64)) return; - if (!IS_ENABLED(CONFIG_X86_64)) + /* Mitigate in hardware if supported */ + if (spec_ctrl_bhi_dis()) return; /* Mitigate KVM by default */ --- a/arch/x86/net/bpf_jit_comp.c +++ b/arch/x86/net/bpf_jit_comp.c @@ -1097,8 +1097,7 @@ static int emit_spectre_bhb_barrier(u8 * /* Insert IBHF instruction */ if ((cpu_feature_enabled(X86_FEATURE_CLEAR_BHB_LOOP) && cpu_feature_enabled(X86_FEATURE_HYPERVISOR)) || - (cpu_feature_enabled(X86_FEATURE_CLEAR_BHB_HW) && - IS_ENABLED(CONFIG_X86_64))) { + cpu_feature_enabled(X86_FEATURE_CLEAR_BHB_HW)) { /* * Add an Indirect Branch History Fence (IBHF). IBHF acts as a * fence preventing branch history from before the fence from @@ -1108,6 +1107,8 @@ static int emit_spectre_bhb_barrier(u8 * * hardware that doesn't need or support it. The REP and REX.W * prefixes are required by the microcode, and they also ensure * that the NOP is unlikely to be used in existing code. + * + * IBHF is not a valid instruction in 32-bit mode. */ EMIT5(0xF3, 0x48, 0x0F, 0x1E, 0xF8); /* ibhf */ }