From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A053D1D63EF; Tue, 27 May 2025 16:50:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748364611; cv=none; b=NB8+O/JcOMWf7mF4jqTbyBt6ghzVjlcPCnB7DivOla20LmeHAYw3JZQwcsZjsGdMjaErLnGypsHymK3JJBtsDHug53+zcFRprM1nDOKaqD1n3Ru5GMubys00KG66m87UyEmBoHLOwwJt9qIL/kiPCgt1qp3V7Bv+5VA3UDjq+4k= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748364611; c=relaxed/simple; bh=Egc74MYzd6jorsL69SbDAR1AHrb0JJAeDDuLQHEqvqY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=YiU36a6OtX2OEG0ON9VCd7RRqylNNZj9aPWqW4szobyV9bXbVFtEl7/ixFGV/PDIWynKo6Wyo5Qi3PoXfZ4nCFcY+ntoBvFVPmxo80VxS41QvYEAKtHQIE3BGhdQYRX6YrTVRmUtM5He5MRrL6QKnqQC0zQPwIjKU4cy/7UWonA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=Ie+LK2Ep; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="Ie+LK2Ep" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2701FC4CEE9; Tue, 27 May 2025 16:50:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1748364611; bh=Egc74MYzd6jorsL69SbDAR1AHrb0JJAeDDuLQHEqvqY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ie+LK2Ep3XR0hiw1/Qqbg0/tqA4Zaj669dPqtroN31uYIMa3ofENdD/hLZiWz5qsh eMo3LFTfeYTijIBfjkmQdCGo0iHWQZsE0A6E4XAAAWCPcbHeQxbqkLaSRbIR2Yj2zV LtZa1gY08JGcTHFH4Z42Dbe1LEKaz0Wu8gObwzSY= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, AngeloGioacchino Del Regno , "=?UTF-8?q?N=C3=ADcolas=20F . =20R . =20A . =20Prado?=" , Daniel Lezcano , Sasha Levin Subject: [PATCH 6.12 080/626] thermal/drivers/mediatek/lvts: Start sensor interrupts disabled Date: Tue, 27 May 2025 18:19:33 +0200 Message-ID: <20250527162448.297675864@linuxfoundation.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250527162445.028718347@linuxfoundation.org> References: <20250527162445.028718347@linuxfoundation.org> User-Agent: quilt/0.68 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 6.12-stable review patch. If anyone has any objections, please let me know. ------------------ From: Nícolas F. R. A. Prado [ Upstream commit 2738fb3ec6838a10d2c4ce65cefdb3b90b11bd61 ] Interrupts are enabled per sensor in lvts_update_irq_mask() as needed, there's no point in enabling all of them during initialization. Change the MONINT register initial value so all sensor interrupts start disabled. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Nícolas F. R. A. Prado Link: https://lore.kernel.org/r/20250113-mt8192-lvts-filtered-suspend-fix-v2-4-07a25200c7c6@collabora.com Signed-off-by: Daniel Lezcano Signed-off-by: Sasha Levin --- drivers/thermal/mediatek/lvts_thermal.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c index 4b3225377e8f8..3295b27ab70d2 100644 --- a/drivers/thermal/mediatek/lvts_thermal.c +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -65,7 +65,6 @@ #define LVTS_HW_FILTER 0x0 #define LVTS_TSSEL_CONF 0x13121110 #define LVTS_CALSCALE_CONF 0x300 -#define LVTS_MONINT_CONF 0x0300318C #define LVTS_MONINT_OFFSET_SENSOR0 0xC #define LVTS_MONINT_OFFSET_SENSOR1 0x180 @@ -929,7 +928,7 @@ static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl) * The LVTS_MONINT register layout is the same as the LVTS_MONINTSTS * register, except we set the bits to enable the interrupt. */ - writel(LVTS_MONINT_CONF, LVTS_MONINT(lvts_ctrl->base)); + writel(0, LVTS_MONINT(lvts_ctrl->base)); return 0; } -- 2.39.5