From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 05C0D27FB10; Tue, 27 May 2025 17:37:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748367440; cv=none; b=Ie9+hHOfSubJlszQUb19Gd9xjl2M1M6dDShHcdGJxzUV+BpFHI5Rs3tQDrKsrfb9BoM7Z+JjZw+vYo2fDqzKCxod0bhPt4bWDKkWYruGIL1+EICAUpS8eZ1e7xeWbTXWEWNCZCy4BFfk63MDcFekgsFg4xs7BAudJDvlSH78yuM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748367440; c=relaxed/simple; bh=K6x+LFmzkRzMkCPs6TPB18QvrUGG/3LElCqBPz9MSJY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=vDZN2b7WLsfKeYSEaEXlIqMHDzWbB1fhc8HuQQrrJ0h+IxylNb5/qcur3yoZbL18mRcNsIBoAxOquUZmTS0pF9uKF7ytVkE3ESbA/kUHWNGVFNDCwWLrc/P3+JG66YYLawq3wH+ZvHiwSgB6QOScmoNQ84yK3om8v5bjL4QF2To= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=jft6BKM7; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="jft6BKM7" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 57FB9C4CEE9; Tue, 27 May 2025 17:37:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1748367439; bh=K6x+LFmzkRzMkCPs6TPB18QvrUGG/3LElCqBPz9MSJY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jft6BKM7cCcMCWRUvFumljFycLKEuEi6A065eqHX0PJFeFl5aGboxQLJemlthMI2q 4NqggsiDPaYQptNyvUvInlfPidkAtBeNeToKn3XqN4oEqyqt3t1nbrMB2GbncJtzld 6G0otZJOUgYIyC9qINolx2LSsH2lGg9IuX0tPrHA= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Paul Burton , Chao-ying Fu , Dragan Mladjenovic , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Serge Semin , Gregory CLEMENT , Daniel Lezcano , Thomas Bogendoerfer , Sasha Levin Subject: [PATCH 6.14 389/783] clocksource: mips-gic-timer: Enable counter when CPUs start Date: Tue, 27 May 2025 18:23:06 +0200 Message-ID: <20250527162528.937239087@linuxfoundation.org> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250527162513.035720581@linuxfoundation.org> References: <20250527162513.035720581@linuxfoundation.org> User-Agent: quilt/0.68 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 6.14-stable review patch. If anyone has any objections, please let me know. ------------------ From: Paul Burton [ Upstream commit 3128b0a2e0cf6e07aa78e5f8cf7dd9cd59dc8174 ] In multi-cluster MIPS I6500 systems there is a GIC in each cluster, each with its own counter. When a cluster powers up the counter will be stopped, with the COUNTSTOP bit set in the GIC_CONFIG register. In single cluster systems, it has been fine to clear COUNTSTOP once in gic_clocksource_of_init() to start the counter. In multi-cluster systems, this will only have started the counter in the boot cluster, and any CPUs in other clusters will find their counter stopped which will break the GIC clock_event_device. Resolve this by having CPUs clear the COUNTSTOP bit when they come online, using the existing gic_starting_cpu() CPU hotplug callback. This will allow CPUs in secondary clusters to ensure that the cluster's GIC counter is running as expected. Signed-off-by: Paul Burton Signed-off-by: Chao-ying Fu Signed-off-by: Dragan Mladjenovic Signed-off-by: Aleksandar Rikalo Reviewed-by: Philippe Mathieu-Daudé Tested-by: Serge Semin Tested-by: Gregory CLEMENT Acked-by: Daniel Lezcano Signed-off-by: Thomas Bogendoerfer Signed-off-by: Sasha Levin --- drivers/clocksource/mips-gic-timer.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clocksource/mips-gic-timer.c b/drivers/clocksource/mips-gic-timer.c index 7907b740497a5..abb685a080a5b 100644 --- a/drivers/clocksource/mips-gic-timer.c +++ b/drivers/clocksource/mips-gic-timer.c @@ -115,6 +115,9 @@ static void gic_update_frequency(void *data) static int gic_starting_cpu(unsigned int cpu) { + /* Ensure the GIC counter is running */ + clear_gic_config(GIC_CONFIG_COUNTSTOP); + gic_clockevent_cpu_init(cpu, this_cpu_ptr(&gic_clockevent_device)); return 0; } @@ -288,9 +291,6 @@ static int __init gic_clocksource_of_init(struct device_node *node) pr_warn("Unable to register clock notifier\n"); } - /* And finally start the counter */ - clear_gic_config(GIC_CONFIG_COUNTSTOP); - /* * It's safe to use the MIPS GIC timer as a sched clock source only if * its ticks are stable, which is true on either the platforms with -- 2.39.5