From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F19532C235B; Mon, 18 Aug 2025 13:54:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755525298; cv=none; b=e4+T+Tm6iO97nQ9nKfIdWqMP4R9WgIsr++vc0FeJNZ0QOIpahEtrtlp4MB6CJMwAACMleJH7ep00jgNHrTStmPgPwWde3fCejqPEBNCt7jTzt64J5TQShb1FUhougssUAMqWx+7LMLLzoCrwM4CCEq6/eOY+fa7CTnEeDLjmJe8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755525298; c=relaxed/simple; bh=G622/99Y4NUBFoMSOd72DHqtBk8YOJB3CmcJR0AqZfk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=IShuLmGPfN0hlupccCsmc4u3PUqEMcffUqQweToSP3JkR6R4VqsTPRB6vYI4qcXTkQa3+nj9WjtZl9hqJxb+587VVUwifpjwjpBlsccl3jn5VpCKq+xiQ3HI5SeA+nmy8ub6ORsIC24GERoj8tmQWJM7OXo8UjlcSl/Q70Hr1TA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=Rjt6iONu; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="Rjt6iONu" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 76742C4CEF1; Mon, 18 Aug 2025 13:54:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1755525297; bh=G622/99Y4NUBFoMSOd72DHqtBk8YOJB3CmcJR0AqZfk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Rjt6iONuFUSITZZUrMNeVUIOrDcd0b3OoYUtK49PgR9g4EQxfFBQLOosw0l4bwuvZ jEGuvg9dqMIDMuE/XCCchoxoD0RpXiTI64CLsM91OP+XQMkeP1afoTbJ8RnR0EyH7x 5Ad9ft6GoJTUIxDsMAVghbXDUB7mGnufjnAceviU= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Jonathan Santos , David Lechner , Andy Shevchenko , Jonathan Cameron , Sasha Levin Subject: [PATCH 6.16 202/570] iio: adc: ad7768-1: Ensure SYNC_IN pulse minimum timing requirement Date: Mon, 18 Aug 2025 14:43:09 +0200 Message-ID: <20250818124513.582929612@linuxfoundation.org> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250818124505.781598737@linuxfoundation.org> References: <20250818124505.781598737@linuxfoundation.org> User-Agent: quilt/0.68 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 6.16-stable review patch. If anyone has any objections, please let me know. ------------------ From: Jonathan Santos [ Upstream commit 7e54d932873d91a55d1b89b7389876d78aeeab32 ] The SYNC_IN pulse width must be at least 1.5 x Tmclk, corresponding to ~2.5 µs at the lowest supported MCLK frequency. Add a 3 µs delay to ensure reliable synchronization timing even for the worst-case scenario. Signed-off-by: Jonathan Santos Reviewed-by: David Lechner Reviewed-by: Andy Shevchenko Link: https://patch.msgid.link/d3ee92a533cd1207cf5c5cc4d7bdbb5c6c267f68.1749063024.git.Jonathan.Santos@analog.com Signed-off-by: Jonathan Cameron Signed-off-by: Sasha Levin --- drivers/iio/adc/ad7768-1.c | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c index 51134023534a..8b414a102864 100644 --- a/drivers/iio/adc/ad7768-1.c +++ b/drivers/iio/adc/ad7768-1.c @@ -252,6 +252,24 @@ static const struct regmap_config ad7768_regmap24_config = { .max_register = AD7768_REG24_COEFF_DATA, }; +static int ad7768_send_sync_pulse(struct ad7768_state *st) +{ + /* + * The datasheet specifies a minimum SYNC_IN pulse width of 1.5 × Tmclk, + * where Tmclk is the MCLK period. The supported MCLK frequencies range + * from 0.6 MHz to 17 MHz, which corresponds to a minimum SYNC_IN pulse + * width of approximately 2.5 µs in the worst-case scenario (0.6 MHz). + * + * Add a delay to ensure the pulse width is always sufficient to + * trigger synchronization. + */ + gpiod_set_value_cansleep(st->gpio_sync_in, 1); + fsleep(3); + gpiod_set_value_cansleep(st->gpio_sync_in, 0); + + return 0; +} + static int ad7768_set_mode(struct ad7768_state *st, enum ad7768_conv_mode mode) { @@ -339,10 +357,7 @@ static int ad7768_set_dig_fil(struct ad7768_state *st, return ret; /* A sync-in pulse is required every time the filter dec rate changes */ - gpiod_set_value(st->gpio_sync_in, 1); - gpiod_set_value(st->gpio_sync_in, 0); - - return 0; + return ad7768_send_sync_pulse(st); } static int ad7768_set_freq(struct ad7768_state *st, -- 2.39.5