From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 606E81662E7; Tue, 26 Aug 2025 14:15:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756217738; cv=none; b=aJaYUM+E8+BHMrjzeoVQ1956R73ws4KqhK8Cjeqx6CNLwgjJ00btBrS48zzC8SYwWCLFZTE/4uCU+pXjylZMSohU4tWH2h8Su1LLwumFZDExvVEfbuctESZU6thw+XMDqbZvcZmBSll8hfz8QHRC76cWZE7I93bFKam+qh26Oxs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756217738; c=relaxed/simple; bh=ndH+JmSoxE6rk6uiLDZMdSSVmtvaBnv695NzwKZZYAE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=mtTY2pK/9N8VqK7ocYih4wXxDhTPNDkL5d6pOexkfads3qu8zoLpmbH+R1Zgu486THpKo9HxqsSu+mfvc71C9MyfFiOiWHmLs51UUVB6qxPN4yP0ZwWcPJAFzPUYCqaijXixnvl4l9rSLKUNPxoMt3CcoR7JM/MJWgpw6h1F03M= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=wgIF4U7V; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="wgIF4U7V" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E8EE7C4CEF1; Tue, 26 Aug 2025 14:15:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1756217738; bh=ndH+JmSoxE6rk6uiLDZMdSSVmtvaBnv695NzwKZZYAE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=wgIF4U7VW6b7zrQdZun4R3mQWuRdXJo6NaUJDwuv7tsyffjz0WdIHngeGLbPqb0U/ CmN9sI/SwCvwW4CSk/IAx69P+o9zyLUYQMnmtO5HK4P4QBsF0AgOkutDC84db4Cgtm va34Ibha5f6biR/ZzLdDhhD4zWsVp83I/9AVfmyI= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Jonathan Santos , David Lechner , Andy Shevchenko , Jonathan Cameron , Sasha Levin Subject: [PATCH 5.10 256/523] iio: adc: ad7768-1: Ensure SYNC_IN pulse minimum timing requirement Date: Tue, 26 Aug 2025 13:07:46 +0200 Message-ID: <20250826110930.742531185@linuxfoundation.org> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250826110924.562212281@linuxfoundation.org> References: <20250826110924.562212281@linuxfoundation.org> User-Agent: quilt/0.68 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 5.10-stable review patch. If anyone has any objections, please let me know. ------------------ From: Jonathan Santos [ Upstream commit 7e54d932873d91a55d1b89b7389876d78aeeab32 ] The SYNC_IN pulse width must be at least 1.5 x Tmclk, corresponding to ~2.5 µs at the lowest supported MCLK frequency. Add a 3 µs delay to ensure reliable synchronization timing even for the worst-case scenario. Signed-off-by: Jonathan Santos Reviewed-by: David Lechner Reviewed-by: Andy Shevchenko Link: https://patch.msgid.link/d3ee92a533cd1207cf5c5cc4d7bdbb5c6c267f68.1749063024.git.Jonathan.Santos@analog.com Signed-off-by: Jonathan Cameron Signed-off-by: Sasha Levin --- drivers/iio/adc/ad7768-1.c | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c index 9580a7f7f73d..883399ad80e0 100644 --- a/drivers/iio/adc/ad7768-1.c +++ b/drivers/iio/adc/ad7768-1.c @@ -202,6 +202,24 @@ static int ad7768_spi_reg_write(struct ad7768_state *st, return spi_write(st->spi, st->data.d8, 2); } +static int ad7768_send_sync_pulse(struct ad7768_state *st) +{ + /* + * The datasheet specifies a minimum SYNC_IN pulse width of 1.5 × Tmclk, + * where Tmclk is the MCLK period. The supported MCLK frequencies range + * from 0.6 MHz to 17 MHz, which corresponds to a minimum SYNC_IN pulse + * width of approximately 2.5 µs in the worst-case scenario (0.6 MHz). + * + * Add a delay to ensure the pulse width is always sufficient to + * trigger synchronization. + */ + gpiod_set_value_cansleep(st->gpio_sync_in, 1); + fsleep(3); + gpiod_set_value_cansleep(st->gpio_sync_in, 0); + + return 0; +} + static int ad7768_set_mode(struct ad7768_state *st, enum ad7768_conv_mode mode) { @@ -287,10 +305,7 @@ static int ad7768_set_dig_fil(struct ad7768_state *st, return ret; /* A sync-in pulse is required every time the filter dec rate changes */ - gpiod_set_value(st->gpio_sync_in, 1); - gpiod_set_value(st->gpio_sync_in, 0); - - return 0; + return ad7768_send_sync_pulse(st); } static int ad7768_set_freq(struct ad7768_state *st, -- 2.39.5