From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E9C62F9992; Tue, 26 Aug 2025 11:28:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756207683; cv=none; b=LhCamg3Hd6vdzReQRMZqdTg3OcqvjiOXolkmMnfg+ar//Tv3lVjRtxw4prJrk34UIhszGitUG80m2FLsFc9rqUvfTuWedv3PC84agMxAx3zk0WSxfXQ05YMG5la0eTlWWDbNek9Z+zoq4i5pDFzyJcYIodjjXl95EIeXnQat3SE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756207683; c=relaxed/simple; bh=KwuFiKuZzQPWpeFbiT4V+A4lGbo/I0+s1VX4RLFJLm4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=oPAYKoXhWttALWKpd0yZwgBtn2G4FvwEAnJhdywYi0EuWlWF2/QDVmcJXkCfGd+qYjPu3UOyqRz9Gynn3JNEiz6AUXNKoIPOKtzCaV3BWQSEXJoCg01DTAP1vPMJ6cKXNblU7ZboXPTxrW0CEUN+OBEd2M1/HYboURtgIM3TVQ4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=t+DObS5C; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="t+DObS5C" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C094FC4CEF1; Tue, 26 Aug 2025 11:28:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1756207683; bh=KwuFiKuZzQPWpeFbiT4V+A4lGbo/I0+s1VX4RLFJLm4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=t+DObS5CrrF0lfB5/kNN7AcWSh0vVNO7FZl8NMUTeM7KF+No4i2p+iy59idiVloZ+ G1hYsTjHaoKePRfxBSbPbWO3ncpk6HTA2KZM46vJIAuckZqaqe6bVrUX9dFb45uNqI w8c+Tmfzw+m+58k2kW+PhASZnVUQaM69D3JXu1H8= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Geraldo Nascimento , Manivannan Sadhasivam , Bjorn Helgaas , Robin Murphy , Sasha Levin Subject: [PATCH 6.16 276/457] PCI: rockchip: Set Target Link Speed to 5.0 GT/s before retraining Date: Tue, 26 Aug 2025 13:09:20 +0200 Message-ID: <20250826110944.202990719@linuxfoundation.org> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250826110937.289866482@linuxfoundation.org> References: <20250826110937.289866482@linuxfoundation.org> User-Agent: quilt/0.68 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.16-stable review patch. If anyone has any objections, please let me know. ------------------ From: Geraldo Nascimento [ Upstream commit 114b06ee108cabc82b995fbac6672230a9776936 ] Rockchip controllers can support up to 5.0 GT/s link speed. But the driver doesn't set the Target Link Speed currently. This may cause failure in retraining the link to 5.0 GT/s if supported by the endpoint. So set the Target Link Speed to 5.0 GT/s in the Link Control and Status Register 2. Fixes: e77f847df54c ("PCI: rockchip: Add Rockchip PCIe controller support") Signed-off-by: Geraldo Nascimento [mani: fixed whitespace warning, commit message rewording, added fixes tag] Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Helgaas Tested-by: Robin Murphy Cc: stable@vger.kernel.org Link: https://patch.msgid.link/0afa6bc47b7f50e2e81b0b47d51c66feb0fb565f.1751322015.git.geraldogabriel@gmail.com Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman --- drivers/pci/controller/pcie-rockchip-host.c | 4 ++++ 1 file changed, 4 insertions(+) --- a/drivers/pci/controller/pcie-rockchip-host.c +++ b/drivers/pci/controller/pcie-rockchip-host.c @@ -342,6 +342,10 @@ static int rockchip_pcie_host_init_port( * Enable retrain for gen2. This should be configured only after * gen1 finished. */ + status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL2); + status &= ~PCI_EXP_LNKCTL2_TLS; + status |= PCI_EXP_LNKCTL2_TLS_5_0GT; + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL2); status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); status |= PCI_EXP_LNKCTL_RL; rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL);