From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7DBA22D24AD; Tue, 30 Sep 2025 14:49:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759243771; cv=none; b=bGLMt4hAaReRDEpT6qGGllkYT3gP1g/IE3PxC0ttHif2nkinXwq/O/AaKztab7vIovZUH7UW11tutt6Xt1BPZgmU0tu4NJNBuVmdIexZtpWxmJyKqLBh+kQZAsL3WbG5yq344m96Os4DU6U0vSEEEmkVwl24Dpxezbllg8qzGvs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759243771; c=relaxed/simple; bh=eMbwBaakxhTTsQTk/h1TVb4rB2unph9ffenU2Fd1JyQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=G2zpMz1Ndzi5JwvcJCwJqnXdFv71UsKqWdIEFEEHk1b1GUajBKpUzhxreXrFNaLMCF64JHSzgTHS7y9o2ju0DzoOERBRIjxlr5Dlajw5YbOwQDel7vJrb/Ei2Pp2jy94Fvrjm6uNcbDx23FN8JlL1yfh3CUrlIpxXRejVavkiWI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=I/x5SkTI; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="I/x5SkTI" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D57BBC4CEF0; Tue, 30 Sep 2025 14:49:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1759243771; bh=eMbwBaakxhTTsQTk/h1TVb4rB2unph9ffenU2Fd1JyQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=I/x5SkTINpBPztJg50irQFnEcNd4n7BjmUvdFz23klcE/3UE19jujNTzch2xXW9dM 9BN8EQRi6dCghKR1EaFQa1Qt4MPv0Np6hMsekHxurlzTjcncnrDcjGxC1HOhC4ZERe I///oUq66U+jI8TG7tygbJcfgwyucKhyu6G60XRo= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Alexander Sverdlin , Alexander Dahl , Miquel Raynal , Sasha Levin Subject: [PATCH 5.4 13/81] mtd: nand: raw: atmel: Respect tAR, tCLR in read setup timing Date: Tue, 30 Sep 2025 16:46:15 +0200 Message-ID: <20250930143820.223742407@linuxfoundation.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250930143819.654157320@linuxfoundation.org> References: <20250930143819.654157320@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 5.4-stable review patch. If anyone has any objections, please let me know. ------------------ From: Alexander Sverdlin [ Upstream commit fd779eac2d659668be4d3dbdac0710afd5d6db12 ] Having setup time 0 violates tAR, tCLR of some chips, for instance TOSHIBA TC58NVG2S3ETAI0 cannot be detected successfully (first ID byte being read duplicated, i.e. 98 98 dc 90 15 76 14 03 instead of 98 dc 90 15 76 ...). Atmel Application Notes postulated 1 cycle NRD_SETUP without explanation [1], but it looks more appropriate to just calculate setup time properly. [1] Link: https://ww1.microchip.com/downloads/aemDocuments/documents/MPU32/ApplicationNotes/ApplicationNotes/doc6255.pdf Cc: stable@vger.kernel.org Fixes: f9ce2eddf176 ("mtd: nand: atmel: Add ->setup_data_interface() hooks") Signed-off-by: Alexander Sverdlin Tested-by: Alexander Dahl Signed-off-by: Miquel Raynal Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman --- drivers/mtd/nand/raw/atmel/nand-controller.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) --- a/drivers/mtd/nand/raw/atmel/nand-controller.c +++ b/drivers/mtd/nand/raw/atmel/nand-controller.c @@ -1312,13 +1312,23 @@ static int atmel_smc_nand_prepare_smccon return ret; /* + * Read setup timing depends on the operation done on the NAND: + * + * NRD_SETUP = max(tAR, tCLR) + */ + timeps = max(conf->timings.sdr.tAR_min, conf->timings.sdr.tCLR_min); + ncycles = DIV_ROUND_UP(timeps, mckperiodps); + totalcycles += ncycles; + ret = atmel_smc_cs_conf_set_setup(smcconf, ATMEL_SMC_NRD_SHIFT, ncycles); + if (ret) + return ret; + + /* * The read cycle timing is directly matching tRC, but is also * dependent on the setup and hold timings we calculated earlier, * which gives: * - * NRD_CYCLE = max(tRC, NRD_PULSE + NRD_HOLD) - * - * NRD_SETUP is always 0. + * NRD_CYCLE = max(tRC, NRD_SETUP + NRD_PULSE + NRD_HOLD) */ ncycles = DIV_ROUND_UP(conf->timings.sdr.tRC_min, mckperiodps); ncycles = max(totalcycles, ncycles);