From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 112192F60D8; Tue, 30 Sep 2025 14:53:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759244002; cv=none; b=uu/isRmHJGFUlomW27vzPmquapxdQ+Z7eEpYbyXdOAyZhdh20HnG53z8Gg6dDz25zxsee1yBouik158jNSDUMcRkHgocOOLJDF6SBH6+7AySLCpKiWhcN3r5CXGE7Lg1aA+wA3HY89CwgAaXEE5a+K+RUBBrl6yu+6f7ZiGSIKc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759244002; c=relaxed/simple; bh=fqLDKpp0Vw7zdu4wfRl6QbwaGPHkD+i39SMJmlPyUAs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=j5bLi00pku8f+NEOeA04QBznt54RiTrLeTpByB/aiOeNJNhgXlqvd8uTYOW7dMtPtiXiOb1h5Ykn3yTG4CkSv9rEvG5IARwCc/F8jaMsi6JuFab6He/muKhsnJWYmgTOqO2kTWnUY6YaZHdBaP3lordU9W1ReA/riOIAzgcbPWg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=Pi31opYi; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="Pi31opYi" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 74B4EC116B1; Tue, 30 Sep 2025 14:53:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1759244001; bh=fqLDKpp0Vw7zdu4wfRl6QbwaGPHkD+i39SMJmlPyUAs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Pi31opYiH+o+g+xNfh9ZZ3XEFhXbdZQ9WBsJfMaQWVR2/gWOuRfO8Xyq1YZzTBIir O4wSHxMQayUIbz7sgUEHheGbYquKnTcWBU1w8OyQupmPnJZ28BMBpzUVhK2KLkh25q K9N849yGl+YWiF/Qyg64pIv/wPycXmRu94KWGN2U= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Lukasz Czapnik , Aleksandr Loktionov , Przemek Kitszel , Simon Horman , Rafal Romanowski , Tony Nguyen , Sasha Levin Subject: [PATCH 5.4 80/81] i40e: add mask to apply valid bits for itr_idx Date: Tue, 30 Sep 2025 16:47:22 +0200 Message-ID: <20250930143823.070824403@linuxfoundation.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250930143819.654157320@linuxfoundation.org> References: <20250930143819.654157320@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 5.4-stable review patch. If anyone has any objections, please let me know. ------------------ From: Lukasz Czapnik [ Upstream commit eac04428abe9f9cb203ffae4600791ea1d24eb18 ] The ITR index (itr_idx) is only 2 bits wide. When constructing the register value for QINT_RQCTL, all fields are ORed together. Without masking, higher bits from itr_idx may overwrite adjacent fields in the register. Apply I40E_QINT_RQCTL_ITR_INDX_MASK to ensure only the intended bits are set. Fixes: 5c3c48ac6bf5 ("i40e: implement virtual device interface") Cc: stable@vger.kernel.org Signed-off-by: Lukasz Czapnik Reviewed-by: Aleksandr Loktionov Signed-off-by: Przemek Kitszel Reviewed-by: Simon Horman Tested-by: Rafal Romanowski Signed-off-by: Tony Nguyen [ Added missing linux/bitfield.h header for FIELD_PREP macro ] Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman --- drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) --- a/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c +++ b/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* Copyright(c) 2013 - 2018 Intel Corporation. */ +#include #include "i40e.h" /*********************notification routines***********************/ @@ -393,7 +394,7 @@ static void i40e_config_irq_link_list(st (qtype << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) | (pf_queue_id << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | BIT(I40E_QINT_RQCTL_CAUSE_ENA_SHIFT) | - (itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT); + FIELD_PREP(I40E_QINT_RQCTL_ITR_INDX_MASK, itr_idx); wr32(hw, reg_idx, reg); }