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From: Jason Gunthorpe <jgg@nvidia.com>
To: Nicolin Chen <nicolinc@nvidia.com>
Cc: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org,
	jean-philippe@linaro.org, miko.lenczewski@arm.com,
	balbirs@nvidia.com, peterz@infradead.org, smostafa@google.com,
	kevin.tian@intel.com, praan@google.com,
	linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev,
	linux-kernel@vger.kernel.org, patches@lists.linux.dev
Subject: Re: [PATCH rfcv2 6/8] iommu/arm-smmu-v3: Populate smmu_domain->invs when attaching masters
Date: Wed, 1 Oct 2025 13:25:16 -0300	[thread overview]
Message-ID: <20251001162516.GE3024065@nvidia.com> (raw)
In-Reply-To: <aNw7UVaktL6/05b8@Asurada-Nvidia>

On Tue, Sep 30, 2025 at 01:19:29PM -0700, Nicolin Chen wrote:
> I see a cleaner way of handling this is to update invs->num_invs
> inside arm_smmu_invs_unref():
> ----------------------------------------------------------------
> @@ -1209,6 +1216,13 @@ size_t arm_smmu_invs_unref(struct arm_smmu_invs *invs,
>                         j++;
>                 }
>         }
> +
> +       /* The lock is required to fence concurrent ATS operations. */
> +       write_lock_irqsave(&invs->rwlock, flags);
> +       /* Trim the size by removing tailing trash entries */
> +       WRITE_ONCE(invs->num_invs, num_invs);
> +       write_unlock_irqrestore(&invs->rwlock, flags);

That seems Ok

It means the arm_smmu_invs_unref() becomes the fence that guarentees
the ATS is stopped for anything marked as trash.

Then the next steps can just be normal RCU and don't need rwlocking.

Jason

  reply	other threads:[~2025-10-01 16:25 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-08 23:26 [PATCH rfcv2 0/8] iommu/arm-smmu-v3: Introduce an RCU-protected invalidation array Nicolin Chen
2025-09-08 23:26 ` [PATCH rfcv2 1/8] iommu/arm-smmu-v3: Clear cmds->num after arm_smmu_cmdq_batch_submit Nicolin Chen
2025-09-09  3:16   ` Balbir Singh
2025-09-09  5:42     ` Nicolin Chen
2025-09-09 22:49       ` Balbir Singh
2025-09-10  2:03         ` Nicolin Chen
2025-09-10  2:56   ` Nicolin Chen
2025-09-08 23:26 ` [PATCH rfcv2 2/8] iommu/arm-smmu-v3: Explicitly set smmu_domain->stage for SVA Nicolin Chen
2025-09-09  3:25   ` Balbir Singh
2025-09-09 22:31   ` Balbir Singh
2025-09-10  2:06     ` Nicolin Chen
2025-09-24 21:07   ` Jason Gunthorpe
2025-09-08 23:26 ` [PATCH rfcv2 3/8] iommu/arm-smmu-v3: Add an inline arm_smmu_domain_free() Nicolin Chen
2025-09-24 21:08   ` Jason Gunthorpe
2025-09-08 23:26 ` [PATCH rfcv2 4/8] iommu/arm-smmu-v3: Introduce a per-domain arm_smmu_invs array Nicolin Chen
2025-09-09 13:01   ` kernel test robot
2025-09-20  0:26   ` Nicolin Chen
2025-09-24 21:29   ` Jason Gunthorpe
2025-09-29 18:52     ` Nicolin Chen
2025-09-30 12:13       ` Jason Gunthorpe
2025-09-08 23:26 ` [PATCH rfcv2 5/8] iommu/arm-smmu-v3: Pre-allocate a per-master invalidation array Nicolin Chen
2025-09-24 21:32   ` Jason Gunthorpe
2025-09-29 19:11     ` Nicolin Chen
2025-09-30 11:55       ` Jason Gunthorpe
2025-09-08 23:27 ` [PATCH rfcv2 6/8] iommu/arm-smmu-v3: Populate smmu_domain->invs when attaching masters Nicolin Chen
2025-09-24 21:42   ` Jason Gunthorpe
2025-09-29 20:52     ` Nicolin Chen
2025-09-30 12:12       ` Jason Gunthorpe
2025-09-30 20:19         ` Nicolin Chen
2025-10-01 16:25           ` Jason Gunthorpe [this message]
2025-10-01 17:16             ` Nicolin Chen
2025-09-08 23:27 ` [PATCH rfcv2 7/8] iommu/arm-smmu-v3: Add arm_smmu_invs based arm_smmu_domain_inv_range() Nicolin Chen
2025-09-24 21:56   ` Jason Gunthorpe
2025-09-29 21:00     ` Nicolin Chen
2025-09-08 23:27 ` [PATCH rfcv2 8/8] iommu/arm-smmu-v3: Perform per-domain invalidations using arm_smmu_invs Nicolin Chen

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