From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC7B122E3E9; Thu, 2 Oct 2025 15:30:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759419059; cv=none; b=F6ZGgWZg1qPuZH+STsu1SPNxUUAtJa8R8tIDs9/xg5acr4A/y54E0s3n27znDzaamSWF5tsv9H04AyyqChm089uaQik968xiO8JTYiXcoDMKiqZ6BZ4atXPhlKdcI/7I0v/TsrZ9U3tylXIxHPWvGiI77Vre87uCLtJ9kjeasZI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1759419059; c=relaxed/simple; bh=RZRhAPwruDBinADBth5fXOP0gpo3S6ZqgzdwnXe25xI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=pV7KgiKdW9ruPcHbbsplAZg/0OZYZEdbTazIulF9xPkyi3WfNKAfEBy97C2X/bhW/5GniONSuxbakBa+tP0gAZbnl9Z+JtbFPq39IKzem39gic+EPKHyRlr5nKZG4DtlBUXTriwpmk3PXp3wfpaZwCQQ7YYezRLR9sOYsF6qUD4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=BJTg+Rgy; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="BJTg+Rgy" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B894DC4CEF9; Thu, 2 Oct 2025 15:30:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1759419058; bh=RZRhAPwruDBinADBth5fXOP0gpo3S6ZqgzdwnXe25xI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BJTg+RgyOKe6pmjDZTGHq0zizZAAoDeqBotApCpsd2WDYvaVCNKq5H6yh3nTaBy3a evmdGCY4u5b4+xYM3ShAc2jFOaY8swmesZWGoD0OJpAeo9p6xsDACB44VXMpIay9kv FoU20f2l6465CRrLSAKE5M8eJ/GLs3EUe6AepiJKYubbStqedW9wJ+qXo9aTa+M89B lhZN+gAFXCIo/QEc8fizQFVf6k2qQqbgXxGy/UpKB6QTSrZQpw+T9WhIR+lPN3U8Tr 7Psn53rwGqR+79pV7YG0NlEA3CX4vOYLeYiwmm/BUZPh6ixt/ruTACc/fc2tRGYNJe WkRwR3/yMAhmw== From: Sasha Levin To: patches@lists.linux.dev, stable@vger.kernel.org Cc: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Conor Dooley , Paul Walmsley , Sasha Levin , paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, linux-riscv@lists.infradead.org Subject: [PATCH AUTOSEL 6.17-6.16] riscv: cpufeature: add validation for zfa, zfh and zfhmin Date: Thu, 2 Oct 2025 11:30:11 -0400 Message-ID: <20251002153025.2209281-24-sashal@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251002153025.2209281-1-sashal@kernel.org> References: <20251002153025.2209281-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.17 Content-Transfer-Encoding: 8bit From: Clément Léger [ Upstream commit 2e2cf5581fccc562f7faf174ffb9866fed5cafbd ] These extensions depends on the F one. Add a validation callback checking for the F extension to be present. Now that extensions are correctly reported using the F/D presence, we can remove the has_fpu() check in hwprobe_isa_ext0(). Signed-off-by: Clément Léger Reviewed-by: Conor Dooley Link: https://lore.kernel.org/r/20250527100001.33284-1-cleger@rivosinc.com Signed-off-by: Paul Walmsley Signed-off-by: Sasha Levin --- LLM Generated explanations, may be completely bogus: Based on my comprehensive analysis of this commit, here is my assessment: **Backport Status: YES** ## Extensive Analysis ### What This Commit Fixes This commit addresses **incorrect CPU feature reporting** for three RISC-V floating-point extensions (ZFA, ZFH, ZFHMIN) that were being exposed to userspace without proper validation that their required dependency (the F extension) is present. ### Code Changes Analysis The commit makes two key changes: 1. **In arch/riscv/kernel/cpufeature.c (lines 477-480)**: - Changes ZFA, ZFH, and ZFHMIN from `__RISCV_ISA_EXT_DATA` to `__RISCV_ISA_EXT_DATA_VALIDATE` - Adds `riscv_ext_f_depends` validation callback (lines 83-90) which checks that the F extension is available before allowing these extensions to be reported - The validation function returns `-EPROBE_DEFER` if F is not present, preventing incorrect feature reporting 2. **In arch/riscv/kernel/sys_hwprobe.c (lines 156-163)**: - Removes the `has_fpu()` conditional check that was previously gating these extensions - This is safe because the validation is now properly handled in cpufeature.c through the validation callbacks ### Why This is a Bug Fix According to the RISC-V ISA specification: - **ZFA** (Additional Floating-Point Instructions) requires F - **ZFH** (Half-Precision Floating-Point) requires F - **ZFHMIN** (Minimal Half-Precision Floating-Point) requires F Without this fix, the kernel could incorrectly report these extensions as available even when the base F extension is not present. This violates the ISA specification and could lead to: 1. **Incorrect userspace behavior**: Applications using hwprobe() might detect these extensions and attempt to use instructions that aren't supported 2. **Illegal instruction exceptions**: If userspace tries to execute these instructions without F support 3. **Inconsistent CPU capability reporting**: The kernel would report capabilities that the hardware doesn't actually support ### Context from Related Commits This commit is part of a larger validation effort: - **e186c28dda11e** (Feb 2025): Introduced `riscv_ext_f_depends` validation for ZFBFMIN - **12e7fbb6a84e6** (Mar 2025): Added F & D extension validation checks - **004961843389e** (Apr 2025): Merged the validation series - **2e2cf5581fccc** (May 2025): This commit - completes the validation by adding it for ZFA/ZFH/ZFHMIN which were missed The commit message states: "Now that extensions are correctly reported using the F/D presence, we can remove the has_fpu() check" - indicating this is cleanup that follows the proper validation infrastructure being put in place. ### Backporting Criteria Assessment ✅ **Fixes a bug affecting users**: Yes - incorrect CPU feature reporting can cause userspace applications to malfunction ✅ **Small and contained**: Yes - only 14 lines changed across 2 files, following an established pattern ✅ **Clear side effects**: No unexpected side effects - makes reporting more correct ✅ **No architectural changes**: No - uses existing validation infrastructure ✅ **Minimal regression risk**: Very low - the change makes feature reporting more conservative (won't report features unless dependencies are met) ✅ **Confined to subsystem**: Yes - only affects RISC-V architecture code ### Conclusion This commit should be backported because it: 1. Fixes incorrect CPU capability reporting that violates the RISC-V ISA specification 2. Prevents potential illegal instruction exceptions in userspace 3. Is small, focused, and low-risk 4. Follows the stable tree rules for important bug fixes with minimal risk 5. Completes a validation series that was already merged upstream The fix ensures RISC-V systems correctly report their capabilities to userspace, which is critical for proper system operation. arch/riscv/kernel/cpufeature.c | 6 +++--- arch/riscv/kernel/sys_hwprobe.c | 14 ++++++-------- 2 files changed, 9 insertions(+), 11 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 743d53415572e..67b59699357da 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -474,10 +474,10 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS), __RISCV_ISA_EXT_DATA(zalrsc, RISCV_ISA_EXT_ZALRSC), __RISCV_ISA_EXT_DATA(zawrs, RISCV_ISA_EXT_ZAWRS), - __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA), + __RISCV_ISA_EXT_DATA_VALIDATE(zfa, RISCV_ISA_EXT_ZFA, riscv_ext_f_depends), __RISCV_ISA_EXT_DATA_VALIDATE(zfbfmin, RISCV_ISA_EXT_ZFBFMIN, riscv_ext_f_depends), - __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH), - __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN), + __RISCV_ISA_EXT_DATA_VALIDATE(zfh, RISCV_ISA_EXT_ZFH, riscv_ext_f_depends), + __RISCV_ISA_EXT_DATA_VALIDATE(zfhmin, RISCV_ISA_EXT_ZFHMIN, riscv_ext_f_depends), __RISCV_ISA_EXT_DATA(zca, RISCV_ISA_EXT_ZCA), __RISCV_ISA_EXT_DATA_VALIDATE(zcb, RISCV_ISA_EXT_ZCB, riscv_ext_zca_depends), __RISCV_ISA_EXT_DATA_VALIDATE(zcd, RISCV_ISA_EXT_ZCD, riscv_ext_zcd_validate), diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c index 0b170e18a2beb..3e9259790816e 100644 --- a/arch/riscv/kernel/sys_hwprobe.c +++ b/arch/riscv/kernel/sys_hwprobe.c @@ -153,14 +153,12 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZVKT); } - if (has_fpu()) { - EXT_KEY(ZCD); - EXT_KEY(ZCF); - EXT_KEY(ZFA); - EXT_KEY(ZFBFMIN); - EXT_KEY(ZFH); - EXT_KEY(ZFHMIN); - } + EXT_KEY(ZCD); + EXT_KEY(ZCF); + EXT_KEY(ZFA); + EXT_KEY(ZFBFMIN); + EXT_KEY(ZFH); + EXT_KEY(ZFHMIN); if (IS_ENABLED(CONFIG_RISCV_ISA_SUPM)) EXT_KEY(SUPM); -- 2.51.0