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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?o6o67opDj1kwpwBkTaQDSGgOl5OuJoHLJA2o4VrbZ+p8Oz7OMxT2hlM51H/H?= =?us-ascii?Q?pCj1+/Q6YaWP5x8t4cHpWFNeYGct8rS2KnquIxEEOsS7XBeP20JCD2TynsD+?= =?us-ascii?Q?zY04BOiqvW3nXKfPRZg2e8k0IgAKXSF+dznZxfRGJuE++74QUw+P/4JyJB0a?= =?us-ascii?Q?ySse5zIBOH5HV55xHZB5o02nrtWVgfaDI1zy2g9EtM2S3XU4rT5il9ffs/sy?= =?us-ascii?Q?vNBjVQTHGLheoiSaf/72hb0OpmzyWCvhZXZ8snlnZauCsTkdo0u1Uo9y/tRu?= =?us-ascii?Q?ljryEFVWisPFpLV2dNSWOXgb0dnfzSan0OJiwjcM/DSdBv10+/0uMJrV+dZJ?= =?us-ascii?Q?vnSIeNCL0Zfb6QUZH30n3De4jsn5YHmCGjyi1cQwLqBrv6UiYCUmnZNddjQL?= =?us-ascii?Q?ybyx43p+JfB46lERDLbD80PnmNCJTmCdYEw/m8CSSBUTgXqo1UzPC1XSVwRz?= =?us-ascii?Q?suXB4qGm7Q+Eo8KQJ4mCkhTbxNHBUqkDxDnNOtBo+HgVkYCGz/esHn76zpfZ?= =?us-ascii?Q?rsLZd9rZQ7jxoRtRFaXrDKGrV+zL2pweXGiXaStb79EXyPbCdYQy2C8ngB7b?= =?us-ascii?Q?gcLwcMCKtpQ0laAp53OLvrebtpjC/S0YOqc15e0tv87Disf6w/K5U7+lgRS9?= =?us-ascii?Q?eO8iD+TK2Od2+8UkdkXlR7JEuRw5urIIF0Hl98FisTfwWjT4KoYFfvP7TpSL?= =?us-ascii?Q?NVbU50aXT6aMmG4sOV/jQVrytfP/dRRgP02bx6jVUy5PFqfqABlZid4O5Ygy?= =?us-ascii?Q?AZqkV/nh4T7Ei4pYBfAvUx6Ye3Lz3W86gn1amAnftnTxI0gwDJy4R9Ve43OD?= =?us-ascii?Q?csFmKwcVa+hizCaRvAOGhtTqVFPjWDtHNrwF32rQ0mMR3MqezYR2PpJZsSOe?= =?us-ascii?Q?OSPhkZPBSwJvODoMO6o1Z8smHTiUiVlHbkgbxs/K90nHRXw/SiODfp0WDv/O?= =?us-ascii?Q?4f+TVYYnoERIxMZft9nhgBTYY3Up2zFRGrna8CVf49IV6waIIZ+L1DniYovx?= =?us-ascii?Q?Gi6AHW7ieSjH4qilXgxtRTDBbdFcuBMbv1Rj1sYkxItMZv2sF6nr3Iz0PXpa?= =?us-ascii?Q?Sm/9oAE5+RmhTvte04Yt1NzBgVYRBhTUUrnSL/SNIwQbfbK3tzB4Z4azvPDM?= =?us-ascii?Q?ov70hQCQ4ZrlMWRmOXRskl8hQ4IfpLXxz+8gAdboG6niWxhjEayTvVk/1DnA?= =?us-ascii?Q?249uvNQzUNdAGGtgsltUdo7E2QQVzi6HYcLV/wDMT73of/m6hoCbnjudgnuK?= =?us-ascii?Q?T0sviTghKaS8r2cqavtiC3yegMIc9Yd5V2HnI03QsWomF+PJZ2s5hICMoOXk?= =?us-ascii?Q?82Fab17c8guSZdjbJnMoO9/EcRJScWbBdU2GnhgIVygql1Z4/5xhAQ8+1l4f?= =?us-ascii?Q?5mzpJ6X0PPzzHQrrxFXfMpddMMOtpIGv0VTmuqf4yc5570nbxPekmfNx10At?= =?us-ascii?Q?fba6tZ/Bc2IzDCE4AyN8sQP7B5NgJyrvXVwDJ2DAxVTN2vC256sN3Ml7Vh5X?= =?us-ascii?Q?K8pyVAnCBR9EPWMcm682e1ZmIbNQkF+3nYs6C2V+TaRT/5Nej664fl23d275?= =?us-ascii?Q?y2xt82s2PhnlehLMHhlDaeUNJ9OPYvPEqBwZH65s?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4e3fbb5f-0108-417a-f353-08de066bbd7e X-MS-Exchange-CrossTenant-AuthSource: BN8PR12MB3604.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Oct 2025 13:08:14.5255 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: mDRPxd7birp0CgEnwJn7uIi5Fk+M2EnA2mh/urCSWXSprDAYUjci0vg+JqvVwV2t X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB8608 On Wed, Oct 08, 2025 at 03:13:32PM +0530, Vasant Hegde wrote: > Jason, > > On 9/3/2025 11:16 PM, Jason Gunthorpe wrote: > > AMD IOMMU v1 is unique in supporting contiguous pages with a variable size > > and it can decode the full 64 bit VA space. Unlike other x86 page tables > > this explicitly does not do sign extension as part of allowing the entire > > 64 bit VA space to be supported. > > I am still catching up w/ entire series.. But here is few fixes needed to boot > this series w/ SME. I got them all, like this - thanks a lot! diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 92095fd17b3899..0b97db94c8c4e0 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -2054,7 +2054,7 @@ static void set_dte_entry(struct amd_iommu *iommu, &pt_info); } - new.data[0] |= pt_info.host_pt_root | + new.data[0] |= __sme_set(pt_info.host_pt_root) | (pt_info.mode & DEV_ENTRY_MODE_MASK) << DEV_ENTRY_MODE_SHIFT; } @@ -2166,7 +2166,7 @@ static int init_gcr3_table(struct iommu_dev_data *dev_data, return ret; pt_iommu_x86_64_hw_info(&pdom->amdv2, &pt_info); - ret = update_gcr3(dev_data, 0, pt_info.gcr3_pt, true); + ret = update_gcr3(dev_data, 0, __sme_set(pt_info.gcr3_pt), true); if (ret) free_gcr3_table(&dev_data->gcr3_info); diff --git a/drivers/iommu/generic_pt/fmt/amdv1.h b/drivers/iommu/generic_pt/fmt/amdv1.h index d7660d4170ef78..26e29b08a9b4ae 100644 --- a/drivers/iommu/generic_pt/fmt/amdv1.h +++ b/drivers/iommu/generic_pt/fmt/amdv1.h @@ -73,22 +73,29 @@ enum { static inline pt_oaddr_t amdv1pt_table_pa(const struct pt_state *pts) { - return oalog2_mul(FIELD_GET(AMDV1PT_FMT_OA, pts->entry), - PT_GRANULE_LG2SZ); + u64 entry = pts->entry; + + if (pts_feature(pts, PT_FEAT_AMDV1_ENCRYPT_TABLES)) + entry = __sme_clr(entry); + return oalog2_mul(FIELD_GET(AMDV1PT_FMT_OA, entry), PT_GRANULE_LG2SZ); } #define pt_table_pa amdv1pt_table_pa /* Returns the oa for the start of the contiguous entry */ static inline pt_oaddr_t amdv1pt_entry_oa(const struct pt_state *pts) { - pt_oaddr_t oa = FIELD_GET(AMDV1PT_FMT_OA, pts->entry); + u64 entry = pts->entry; + pt_oaddr_t oa; - if (FIELD_GET(AMDV1PT_FMT_NEXT_LEVEL, pts->entry) == - AMDV1PT_FMT_NL_SIZE) { + if (pts_feature(pts, PT_FEAT_AMDV1_ENCRYPT_TABLES)) + entry = __sme_clr(entry); + oa = FIELD_GET(AMDV1PT_FMT_OA, entry); + + if (FIELD_GET(AMDV1PT_FMT_NEXT_LEVEL, entry) == AMDV1PT_FMT_NL_SIZE) { unsigned int sz_bits = oaffz(oa); oa = oalog2_set_mod(oa, 0, sz_bits); - } else if (PT_WARN_ON(FIELD_GET(AMDV1PT_FMT_NEXT_LEVEL, pts->entry) != + } else if (PT_WARN_ON(FIELD_GET(AMDV1PT_FMT_NEXT_LEVEL, entry) != AMDV1PT_FMT_NL_DEFAULT)) return 0; return oalog2_mul(oa, PT_GRANULE_LG2SZ); diff --git a/drivers/iommu/generic_pt/fmt/x86_64.h b/drivers/iommu/generic_pt/fmt/x86_64.h index be2a0a770f903f..d33b2fcd865b84 100644 --- a/drivers/iommu/generic_pt/fmt/x86_64.h +++ b/drivers/iommu/generic_pt/fmt/x86_64.h @@ -79,14 +79,22 @@ enum { static inline pt_oaddr_t x86_64_pt_table_pa(const struct pt_state *pts) { - return oalog2_mul(FIELD_GET(X86_64_FMT_OA, pts->entry), + u64 entry = pts->entry; + + if (pts_feature(pts, PT_FEAT_X86_64_AMD_ENCRYPT_TABLES)) + entry = __sme_clr(entry); + return oalog2_mul(FIELD_GET(X86_64_FMT_OA, entry), PT_TABLEMEM_LG2SZ); } #define pt_table_pa x86_64_pt_table_pa static inline pt_oaddr_t x86_64_pt_entry_oa(const struct pt_state *pts) { - return oalog2_mul(FIELD_GET(X86_64_FMT_OA, pts->entry), + u64 entry = pts->entry; + + if (pts_feature(pts, PT_FEAT_X86_64_AMD_ENCRYPT_TABLES)) + entry = __sme_clr(entry); + return oalog2_mul(FIELD_GET(X86_64_FMT_OA, entry), PT_GRANULE_LG2SZ); } #define pt_entry_oa x86_64_pt_entry_oa