[PATCH AUTOSEL 6.17-6.16] spi: spi-qpic-snand: handle 'use_ecc' parameter of qcom_spi_config_cw_read()

[Sasha Levin <sashal@kernel.org>]

From: Gabor Juhos <j4g8y7@gmail.com>

[ Upstream commit 9c45f95222beecd6a284fd1284d54dd7a772cf59 ]

During raw read, neither the status of the ECC correction nor the erased
state of the codeword gets checked by the qcom_spi_read_cw_raw() function,
so in case of raw access reading the corresponding registers via DMA is
superfluous.

Extend the qcom_spi_config_cw_read() function to evaluate the existing
(but actually unused) 'use_ecc' parameter, and configure reading only
the flash status register when ECC is not used.

With the change, the code gets in line with the corresponding part of
the config_nand_cw_read() function in the qcom_nandc driver.

Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://patch.msgid.link/20250808-qpic-snand-handle-use_ecc-v1-1-67289fbb5e2f@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---

LLM Generated explanations, may be completely bogus:

Based on my comprehensive analysis of this commit, here is my
assessment:

## Backport Recommendation: **YES**

### Analysis Summary:

**Context & History:**
This commit fixes a code correctness issue in the spi-qpic-snand driver
(added in v6.17, Feb 2025). The `qcom_spi_config_cw_read()` function had
a `use_ecc` parameter since the driver's inception, but it was
completely ignored - the function always read both ECC-related registers
regardless of whether ECC was being used.

**Technical Details:**
The change modifies lines 491-500 in `drivers/spi/spi-qpic-snand.c`:

**Before:** Always reads 3 registers via DMA:
- `NAND_FLASH_STATUS` + `NAND_BUFFER_STATUS` (2 registers)
- `NAND_ERASED_CW_DETECT_STATUS` (1 register)

**After:** Conditionally reads based on `use_ecc`:
- When `use_ecc=true`: Reads all 3 registers (normal ECC-enabled reads)
- When `use_ecc=false`: Reads only `NAND_FLASH_STATUS` (raw reads)

**Why This Matters:**
1. **Code Correctness:** During raw reads (`use_ecc=false`), the
   `qcom_spi_check_raw_flash_errors()` function (line 557-571) only
   checks the flash status register, never the ECC registers. Reading
   those ECC registers via DMA is "superfluous" as the commit message
   states.

2. **Established Pattern:** This aligns with the qcom_nandc driver's
   `config_nand_cw_read()` function, which has had this exact same
   conditional logic since 2018 (commit 5bc36b2bf6e2c8). That commit's
   message explained: "For raw reads, there won't be any ECC failure but
   the operational failures are possible, so schedule the
   NAND_FLASH_STATUS read."

3. **Already Backported:** The commit shows `[ Upstream commit
   9c45f95222bee ]` and `Signed-off-by: Sasha Levin
   <sashal@kernel.org>`, indicating it was already selected by AUTOSEL.

**Backport Justification:**

✅ **Pros:**
- Small, contained change (11 lines, 1 file)
- Fixes code correctness (parameter was being ignored)
- Removes unnecessary DMA operations (optimization)
- Aligns with well-established pattern from related driver
- Very low regression risk
- Already reviewed and approved by Konrad Dybcio and Mark Brown
- No follow-up fixes or reverts since Aug 8, 2025

❌ **Cons:**
- No explicit `Fixes:` tag
- No `Cc: stable@vger.kernel.org` tag
- Not fixing a critical user-visible bug
- More optimization/cleanup than bug fix
- Limited impact (Qualcomm-specific hardware only)

**Conclusion:**
While this doesn't fix a critical bug, it fixes a code correctness issue
where a function parameter was being completely ignored. The unnecessary
DMA operations during raw reads waste resources and could potentially
cause subtle timing or performance issues. The change is safe, well-
reviewed, and follows the established pattern from the mature qcom_nandc
driver. The fact that AUTOSEL has already selected it confirms its
suitability for stable backporting.

 drivers/spi/spi-qpic-snand.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/spi-qpic-snand.c b/drivers/spi/spi-qpic-snand.c
index 780abb967822a..5a247eebde4d9 100644
--- a/drivers/spi/spi-qpic-snand.c
+++ b/drivers/spi/spi-qpic-snand.c
@@ -494,9 +494,14 @@ qcom_spi_config_cw_read(struct qcom_nand_controller *snandc, bool use_ecc, int c
 	qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
 	qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
 
-	qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 2, 0);
-	qcom_read_reg_dma(snandc, NAND_ERASED_CW_DETECT_STATUS, 1,
-			  NAND_BAM_NEXT_SGL);
+	if (use_ecc) {
+		qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 2, 0);
+		qcom_read_reg_dma(snandc, NAND_ERASED_CW_DETECT_STATUS, 1,
+				  NAND_BAM_NEXT_SGL);
+	} else {
+		qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 1,
+				  NAND_BAM_NEXT_SGL);
+	}
 }
 
 static int qcom_spi_block_erase(struct qcom_nand_controller *snandc)
-- 
2.51.0