From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A2F22C11E5; Mon, 13 Oct 2025 14:47:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760366876; cv=none; b=tRE/eutUtS+HfzXn7MvkpsnUuZi/vpUgW77LiSHA9Dcdu07IRwW/sTGZJzjlS924YQNTqSChkGWqV4gSl3sxd7yQ9EJJ2MqOQZKhyRx5PKScAkEjnPidIqbi1WZ4xpKi9oAPpDFAUIAsZQ7VznI7wXwaUk7R1CAX2jqtHzf9hJ8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760366876; c=relaxed/simple; bh=sSnMqToS4j05OlSPtPL8oTOFl8BcC7WNoJhgKTr04RY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XNnsGtFI9SPQiatHVivCB9d3jXYT+cOZSq05Fx+sNAFxKo4qkw+pRoH+y13rvSc2yzbbCaaEfqfwqFWIOYEMEiK86hzmFdfAWQpHbarGHlxiq/08pwJ+EM1LxpKjBzVkmo4tCVFfm0hFOeanQJHyyB+VtbGV0UotR1eAGlMi878= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=LF0j1U+1; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="LF0j1U+1" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 196B1C4CEE7; Mon, 13 Oct 2025 14:47:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1760366876; bh=sSnMqToS4j05OlSPtPL8oTOFl8BcC7WNoJhgKTr04RY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LF0j1U+1Ae35LxGNKK/vz+Vkrx1e0bAKXRt2N/aO26riIJDmHZgVQEp0CG2oeyYo6 wXO1OwkcsiElNP+2fum9iI8jTWnK/UHRAkqTYQP2D/yTHY0bZUebS53SthfT+TR0a3 WmYdo9ibXtKPSIi7HC2iBHtDr9TiwAn2iVaSpBbE= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Pierre Gondois , Conor Dooley , Palmer Dabbelt , Sudeep Holla , Wen Yang Subject: [PATCH 6.1 003/196] cacheinfo: Use RISC-Vs init_cache_level() as generic OF implementation Date: Mon, 13 Oct 2025 16:42:56 +0200 Message-ID: <20251013144314.681951389@linuxfoundation.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251013144314.549284796@linuxfoundation.org> References: <20251013144314.549284796@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.1-stable review patch. If anyone has any objections, please let me know. ------------------ From: Pierre Gondois commit c3719bd9eeb2edf84bd263d662e36ca0ba262a23 upstream. RISC-V's implementation of init_of_cache_level() is following the Devicetree Specification v0.3 regarding caches, cf.: - s3.7.3 'Internal (L1) Cache Properties' - s3.8 'Multi-level and Shared Cache Nodes' Allow reusing the implementation by moving it. Also make 'levels', 'leaves' and 'level' unsigned int. Signed-off-by: Pierre Gondois Reviewed-by: Conor Dooley Acked-by: Palmer Dabbelt Link: https://lore.kernel.org/r/20230104183033.755668-2-pierre.gondois@arm.com Signed-off-by: Sudeep Holla Signed-off-by: Wen Yang Signed-off-by: Greg Kroah-Hartman --- arch/riscv/kernel/cacheinfo.c | 39 ------------------------------------- drivers/base/cacheinfo.c | 44 ++++++++++++++++++++++++++++++++++++++++++ include/linux/cacheinfo.h | 1 3 files changed, 46 insertions(+), 38 deletions(-) --- a/arch/riscv/kernel/cacheinfo.c +++ b/arch/riscv/kernel/cacheinfo.c @@ -115,44 +115,7 @@ static void fill_cacheinfo(struct cachei int init_cache_level(unsigned int cpu) { - struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); - struct device_node *np = of_cpu_device_node_get(cpu); - struct device_node *prev = NULL; - int levels = 0, leaves = 0, level; - - if (of_property_read_bool(np, "cache-size")) - ++leaves; - if (of_property_read_bool(np, "i-cache-size")) - ++leaves; - if (of_property_read_bool(np, "d-cache-size")) - ++leaves; - if (leaves > 0) - levels = 1; - - prev = np; - while ((np = of_find_next_cache_node(np))) { - of_node_put(prev); - prev = np; - if (!of_device_is_compatible(np, "cache")) - break; - if (of_property_read_u32(np, "cache-level", &level)) - break; - if (level <= levels) - break; - if (of_property_read_bool(np, "cache-size")) - ++leaves; - if (of_property_read_bool(np, "i-cache-size")) - ++leaves; - if (of_property_read_bool(np, "d-cache-size")) - ++leaves; - levels = level; - } - - of_node_put(np); - this_cpu_ci->num_levels = levels; - this_cpu_ci->num_leaves = leaves; - - return 0; + return init_of_cache_level(cpu); } int populate_cache_leaves(unsigned int cpu) --- a/drivers/base/cacheinfo.c +++ b/drivers/base/cacheinfo.c @@ -223,8 +223,52 @@ static int cache_setup_of_node(unsigned return 0; } + +int init_of_cache_level(unsigned int cpu) +{ + struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); + struct device_node *np = of_cpu_device_node_get(cpu); + struct device_node *prev = NULL; + unsigned int levels = 0, leaves = 0, level; + + if (of_property_read_bool(np, "cache-size")) + ++leaves; + if (of_property_read_bool(np, "i-cache-size")) + ++leaves; + if (of_property_read_bool(np, "d-cache-size")) + ++leaves; + if (leaves > 0) + levels = 1; + + prev = np; + while ((np = of_find_next_cache_node(np))) { + of_node_put(prev); + prev = np; + if (!of_device_is_compatible(np, "cache")) + break; + if (of_property_read_u32(np, "cache-level", &level)) + break; + if (level <= levels) + break; + if (of_property_read_bool(np, "cache-size")) + ++leaves; + if (of_property_read_bool(np, "i-cache-size")) + ++leaves; + if (of_property_read_bool(np, "d-cache-size")) + ++leaves; + levels = level; + } + + of_node_put(np); + this_cpu_ci->num_levels = levels; + this_cpu_ci->num_leaves = leaves; + + return 0; +} + #else static inline int cache_setup_of_node(unsigned int cpu) { return 0; } +int init_of_cache_level(unsigned int cpu) { return 0; } #endif int __weak cache_setup_acpi(unsigned int cpu) --- a/include/linux/cacheinfo.h +++ b/include/linux/cacheinfo.h @@ -80,6 +80,7 @@ struct cpu_cacheinfo { struct cpu_cacheinfo *get_cpu_cacheinfo(unsigned int cpu); int init_cache_level(unsigned int cpu); +int init_of_cache_level(unsigned int cpu); int populate_cache_leaves(unsigned int cpu); int cache_setup_acpi(unsigned int cpu); bool last_level_cache_is_valid(unsigned int cpu);